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318589-005 quad-core intel? xeon? processor 5400 series datasheet august 2008
2 quad-core intel? xeon? processor 5400 series datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual proper ty rights is granted by this document. except as provided in intel's terms and condit ions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, rela ting to sale and/or use of intel products including liability or warranties relating to fitness for a particul ar purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising fro m future changes to them. the quad-core intel? xeon? processor 5400 series may contain desi gn defects or errors known as errata which may cause the product to deviate from published specifications. cu rrent characterized errata are available on request. 64-bit computing on intel architectu re requires a computer system with a processor, chipset, bios, operating system, device drivers and applicatio ns enabled for intel ? 64 architecture. processors will not operat e (including 32-bit operation) without an intel ? 64 architecture-enabled bios. performance will vary depending on your hardware and software configurations. consult with your system vendor for more information. intel? virtualization technology requires a computer system with an enabled intel? processor, bios, virtual machine monitor (vmm) and, for some uses, certain computer system software enabled for it. functionality, performance or other benefits will va ry depending on hardware and software configurations and may require a bios update. software applications may not be compatible with all operating systems. please check with your application vendor. contact your local intel sales office or your distributor to obta in the latest specifications an d before placing your product o rder. intel, pentium, intel xeon, intel speedstep technology, intel core, and the intel logo are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be cl aimed as the property of others. copyright ? 2007-2008, intel corporation.
quad-core intel? xeon? processor 5400 series datasheet 3 contents 1introduction .............................................................................................................. 9 1.1 terminology ..................................................................................................... 10 1.2 state of data .................................................................................................... 13 1.3 references ....................................................................................................... 13 2 quad-core intel? xeon? processor 54 00 series electrical specifications ................ 15 2.1 front side bus and gtlref ................................................................................ 15 2.2 power and ground lands.................................................................................... 16 2.3 decoupling guidelines ........................................................................................ 16 2.3.1 vcc decoupling...................................................................................... 16 2.3.2 vtt decoupling ...................................................................................... 16 2.3.3 front side bus agtl+ decoupling ............................................................ 16 2.4 front side bus clock (bclk[1:0]) and processo r clocking ....................................... 17 2.4.1 front side bus frequency select signals (bsel[2:0]) .................................. 17 2.4.2 pll power supply ................................................................................... 18 2.5 voltage identification (vid) ....................... ......................................................... 18 2.6 reserved, unused, and test signals..................................................................... 21 2.7 front side bus signal groups .............................................................................. 22 2.8 cmos asynchronous and open drain asynchrono us signals .................................... 24 2.9 test access port (tap) connection....................................................................... 24 2.10 platform environmental control interface (pec i) dc specifications........................... 24 2.10.1 dc characteristics .................................................................................. 24 2.10.2 input device hysteresis .......................................................................... 25 2.11 mixing processors.............................................................................................. 26 2.12 absolute maximum and minimum ratings ............................................................. 26 2.13 processor dc specifications ................................................................................ 27 2.13.1 flexible motherboard guidelines (fmb) ...................................................... 27 2.13.2 vcc overshoot specification .................................................................... 38 2.13.3 die voltage validation ............................................................................. 39 2.14 agtl+ fsb specifications................................................................................... 39 3 mechanical specifications ........................................................................................ 43 3.1 package mechanical drawings ...................... ....................................................... 43 3.2 processor component keepout zones................................................................... 47 3.3 package loading specifications ........................................................................... 47 3.4 package handling guidelines............................................................................... 48 3.5 package insertion specifications.......................................................................... 48 3.6 processor mass specifications ............................................................................. 48 3.7 processor materials............................................................................................ 48 3.8 processor markings............................................................................................ 48 3.9 processor land coordinates ................................................................................ 49 4land listing ............................................................................................................. 51 4.1 quad-core intel? xeon? processor 5400 series pin assignments ........................... 51 4.1.1 land listing by land name ...................................................................... 51 4.1.2 land listing by land number ................................................................... 61 5 signal definitions .................................................................................................... 71 5.1 signal definitions .............................................................................................. 71 6 thermal specifications ............................................................................................ 79 6.1 package thermal specifications ........................................................................... 79 6.1.1 thermal specifications ............................................................................ 79 6.1.2 thermal metrology ................................................................................. 90 6.2 processor thermal features ................................................................................ 90
4 quad-core intel? xeon? processor 5400 series datasheet 6.2.1 intel ? thermal monitor features...............................................................90 6.2.2 on-demand mode ...................................................................................92 6.2.3 prochot# signal ..................................................................................93 6.2.4 forcepr# signal ...................................................................................93 6.2.5 thermtrip# signal ................................................................................94 6.3 platform environment control interface (peci) ......................................................94 6.3.1 introduction ...........................................................................................94 6.3.2 peci specifications .................................................................................96 7features ..................................................................................................................97 7.1 power-on configuration options ..........................................................................97 7.2 clock control and low power states .....................................................................97 7.2.1 normal state .........................................................................................98 7.2.2 halt or extended halt state...................................................................98 7.2.3 stop-grant state .................................................................................. 100 7.2.4 extended halt snoop or halt snoop state, stop grant snoop state......................................................................... 101 7.3 enhanced intel speedstep? technology ............................................................. 101 8 boxed processor specifications .............................................................................. 103 8.1 introduction .................................................................................................... 103 8.2 mechanical specifications ............................. ..................................................... 105 8.2.1 boxed processor heat sink dimensions (cek)........................................... 105 8.2.2 boxed processor heat sink weight .......................................................... 113 8.2.3 boxed processor retention mechanism and heat sink support (cek)...................................................................................... 113 8.3 electrical requirements .................................................................................... 113 8.3.1 fan power supply (active cek)............................................................... 113 8.3.2 boxed processor cooling requirements.................................................... 114 8.4 boxed processor contents................................................................................. 115 9 debug tools specifications .................................................................................... 117 9.1 debug port system requirements ...................................................................... 117 9.2 target system implementation.......................................................................... 117 9.2.1 system implementation......................................................................... 117 9.3 logic analyzer interface (lai) ........................................................................... 117 9.3.1 mechanical considerations ..................... ................................................ 118 9.3.2 electrical considerations ........................ ................................................ 118
quad-core intel? xeon? processor 5400 series datasheet 5 figures 2-1 input device hysteresis ..................................................................................... 25 2-2 quad-core intel? xeon? processor x5482 load current versus time ...................... 30 2-3 quad-core intel? xeon? processor x5400 series load current versus time ............ 31 2-4 quad-core intel? xeon? processor e5400 series load current versus time............. 31 2-5 quad-core intel? xeon? processor l5400 series load current versus time ............. 32 2-6 vcc static and transient tolerance load lines ... ................................................... 34 2-7 quad-core intel? xeon? processor x5482 vcc static and transient tolerance load lines ........................................................................... 35 2-8 quad-core intel? xeon? processor x5400 series vcc static and transient tolerance load lines ........................................................................... 36 2-9 quad-core intel? xeon? processor e5400 series vcc static and transient tolerance load lines ........................................................................... 36 2-10 quad-core intel? xeon? processor l5 400 series vcc static and transient tolerance load lines ......................................................................................... 37 2-11 vcc overshoot example waveform...................................................................... 39 2-12 electrical test circuit ........... .............................................................................. 41 2-13 differential clock waveform................................................................................ 41 2-14 differential clock crosspoint specification...... ....................................................... 42 2-15 differential rising and falling edge rates ......... ............ ........... .......... ........... ........ 42 3-1 processor package assembly sketch .................................................................... 43 3-2 quad-core intel? xeon? processor 5400 series package drawing (sheet 1 of 3) ...... 44 3-3 quad-core intel? xeon? processor 5400 series package drawing (sheet 2 of 3) ...... 45 3-4 quad-core intel? xeon? processor 5400 series package drawing (sheet 3 of 3) ...... 46 3-5 processor top-side markings (example)................................................................ 49 3-6 processor land coordinates, top view.................................................................. 49 3-7 processor land coordinates, bottom view............................................................. 50 6-1 quad-core intel? xeon? processor x5492 and x5482 (c-step)thermal profile ......... 81 6-2 quad-core intel? xeon? processor x5400 se ries thermal profiles a and b .............. 83 6-3 quad-core intel? xeon? processor e5400 series thermal profile ........................... 86 6-4 quad-core intel? xeon? processor l5400 series thermal profile............................ 87 6-5 quad-core intel? xeon? processor l5408 thermal profile ..................................... 89 6-6 case temperature (tcase) measurement location ................................................ 90 6-7 intel? thermal monitor 2 frequency and voltag e ordering ..................................... 92 6-8 quad-core intel? xeon? processor 5400 series peci topology .............................. 94 6-9 conceptual fan control diagram of peci-based platforms ....................................... 95 7-1 stop clock state machine ............................ ..................................................... 100 8-1 boxed quad-core intel? xeon? processor 5400 series 1u passive/3u+ active combination heat sink (with removable fan) .................... 104 8-2 boxed quad-core intel? xeon? processor 5400 series 2u passive heat sink ......... 104 8-3 2u passive quad-core intel? xeon? processor 5400 series thermal solution (exploded view) ..................................................................... 105 8-4 top side board keepout zones (part 1) .............................................................. 106 8-5 top side board keepout zones (part 2) .............................................................. 107 8-6 bottom side board keepout zones..................................................................... 108 8-7 board mounting-hole keepout zones ................................................................. 109 8-8 volumetric height keep-ins .............................................................................. 110 8-9 4-pin fan cable connector (for active cek heat sink) ......................................... 111 8-10 4-pin base board fan header (for active cek heat sink)...................................... 112 8-11 fan cable connector pin out for 4-pin active cek thermal solution ....................... 114
6 quad-core intel? xeon? processor 5400 series datasheet tables 1-1 quad-core intel? xeon? processor 5400 series ...................................................10 2-1 core frequency to fsb multiplier configuration .... ..................................................17 2-2 bsel[2:0] frequency table .................................................................................18 2-3 voltage identification definition ...........................................................................20 2-4 loadline selection truth table for ll_id[1:0] ... .....................................................21 2-5 market segment selection truth table for ms_id[1:0] ...........................................21 2-6 fsb signal groups .............................................................................................22 2-7 agtl+ signal description table ...........................................................................23 2-8 non agtl+ signal description table.....................................................................23 2-9 signal reference voltages...................................................................................23 2-10 peci dc electrical limits.......................... ...........................................................25 2-11 processor absolute maximum ratings .............. .....................................................27 2-12 voltage and current specifications ................ .......................................................28 2-13 quad-core intel? xeon? pr ocessor x5482 vcc static and transient tolerance............................................................................................32 2-14 quad-core intel? xeon? processor x5400 series, quad-core intel? xeon? processor e5400 series, quad-core intel? xeon? processor l5400 series vcc static and transient tolerance ......................................................................33 2-15 agtl+ signal group dc specifications..................................................................37 2-16 cmos signal input/output group and tap signal group dc specifications ...............................................................................................38 2-17 open drain output signal grou p dc specifications .................................................38 2-18 vcc overshoot specifications ..............................................................................38 2-19 agtl+ bus voltage definitions ..................... .......................................................40 2-20 fsb differential bclk specifications .....................................................................40 3-1 package loading specifications ..................... .......................................................47 3-2 package handling guidelines ...............................................................................48 3-3 processor materials ............................................................................................48 4-1 land listing by land name .................................................................................51 4-2 land listing by land number ..............................................................................61 5-1 signal definitions...............................................................................................71 6-1 quad-core intel? xeon? processo r x5492 and x5482 (c-step) thermal specifications ....................................................................................................81 6-2 quad-core intel? xeon? processor x5492 and x5482 (c-step)thermal profile table .82 6-3 quad-core intel? xeon? processor x5400 series thermal specifications .................83 6-4 quad-core intel? xeon? processor x5400 series thermal profile a table ................84 6-5 quad-core intel? xeon? processor x5400 series thermal profile b table ................85 6-6 quad-core intel? xeon? processor e5400 seri es thermal specifications..................85 6-7 quad-core intel? xeon? processor e5400 series thermal profile table ...................86 6-8 quad-core intel? xeon? processor l5400 series thermal specifications ..................87 6-9 quad-core intel? xeon? processor l5400 series thermal profile table....................88 6-10 quad-core intel? xeon? processor l5408 thermal specifications ...........................88 6-11 quad-core intel? xeon? processor l5408 thermal profile table .............................89 6-12 gettemp0() gettemp1()error codes ....................................................................96 7-1 power-on configuration option lands...................................................................97 7-2 extended halt maximum power ..........................................................................99 8-1 pwm fan frequency specifications for 4-pin active cek thermal solution................ 114 8-2 fan specifications for 4-pin active cek therma l solution....................................... 114 8-3 fan cable connector pin out for 4-pin active cek thermal solution........................ 114
quad-core intel? xeon? processor 5400 series datasheet 7 revision history revision description date 001 initial release november 2007 002 added product information for the quad-core intel? xeon? processor l5408. march 2008 003 added product information for the quad-core intel? xeon? processor l5400 series. april 2008 004 corrected l1 cache size introduced x5492 updated x5482 power levels on e-step august 2008 005 maintains change bars from version 004. denoted in the introduction section that e-step of the x5482 falls into the 120w x5400 family. added x5492 processor to table 7- 1 and in introduction section. august 2008
8 quad-core intel? xeon? processor 5400 series datasheet
9 1 introduction the quad-core intel? xeon? processor 5400 se ries is a server/workstation processor utilizing four 45-nm hi-k next generation intel? core? microarchitecture cores. the processor is manufactured on intel?s 45 nanometer process technology combining high performance with the power efficiencies of a low-power microarchitecture. the quad- core intel? xeon? processor 5400 series ma intains the tradition of compatibility with ia-32 software. some key features include on-die, primary 32-kb instruction cache and 32-kb write-back data cache in each core and 12 mb (2 x 6mb) level 2 cache with intel ? advanced smart cache architecture. the processors? data prefetch logic speculatively fetches data to the l2 cache before an l1 cache requests occurs, resulting in reduced effective bus latency and improved performance. the 1066 mhz front side bus (fsb) is a quad-pumped bus running off a 266 mhz system clock making 8.5 gbytes per second data transfer rates possible. the 1333 mhz front side bus (fsb) is a quad-pumped bus running off a 333 mh z system clock making 10.66 gbytes per second data transfer rates possible. the 1600 mhz front side bus (fsb) is a quad- pumped bus running off a 400 mhz system cl ock making 12.80 gbytes per second data transfer rates possible. enhanced thermal and power management capabilities are implemented including intel ? thermal monitor 1, intel? thermal monitor 2 and enhanced intel speedstep ? technology. these technologies are targeted for dual processor configurations in enterprise environments. intel ? thermal monitor 1 and intel? thermal monitor provide efficient and effective cooling in hi gh temperature situations. enhanced intel speedstep technology provides power management capabilities to servers and workstations. quad-core intel? xeon? processor 5400 series features include intel ? wide dynamic execution, enhanced floating point and mult i-media units, streaming simd extensions 2 (sse2), streaming simd extensions 3 (sse3), and streaming simd extensions 4.1 (sse4.1). advanced dynamic execution improves speculative execution and branch prediction internal to the processor. the floating point and multi-media units include 128-bit wide registers and a separate register for data movement. sse3 instructions provide highly efficient double-precision floating point, simd integer, and memory management operations. the quad-core intel? xeon? processor 5400 series support intel ? 64 architecture as an enhancement to intel's ia-32 architecture. this enhancement allows the processor to execute operating systems an d applications written to take advantage of the 64-bit extension technology. further details on intel ? 64 architecture and its programming model can be found in the intel ? 64 and ia-32 architectures software developer?s manual, at http://www.intel.com/products/processor/manuals/ . in addition, the quad-core intel? xeon? processor 5400 series supports the execute disable bit functionality. when used in conj unction with a supporting operating system, execute disable allows memory to be marked as executable or non executable. this feature can prevent some classes of viruses that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. further details on execute disable can be found at http://www.intel.com/cd/ids/developer/asmo- na/eng/149308.htm . the quad-core intel? xeon? processor 5400 series support intel ? virtualization technology for hardware-assisted virtualization within the processor. intel virtualization technology is a set of hardware enhancements that can improve virtualization
10 solutions. intel virtualization technology is used in conjunction with virtual machine monitor software enabling multiple, independent software environments inside a single platform. further details on intel virtualization technology can be found at http://developer.intel.com/technology/platform-technology/virtualization/index.htm . the quad-core intel? xeon? processor 5400 series is intended for high performance server and workstation systems. the quad -core intel? xeon? processor 5400 series supports a dual independent bus (dib) archit ecture with one processor on each bus, up to two processor sockets in a system. the dib architecture provides improved performance by allowing increased fsb sp eeds and bandwidth. the quad-core intel? xeon? processor 5400 series will be packaged in an fc-lga land grid array package with 771 lands for improved power delivery. it utilizes a surface mount lga771 socket that supports direct socket loading (dsl). the quad-core intel? xeon? processor 5400 series-based platforms implement independent core voltage (v cc ) power planes for each processor. fsb termination voltage (v tt ) is shared and must connect to all fsb agents. the processor core voltage utilizes power delivery guidelines specified by vrm/evrd 11.0 and its associated load line (see voltage regulator module (vrm) and enterprise voltage regulator-down (evrd) 11.0 design guidelines for further details). vrm/evrd 11.0 will support the power requirements of all frequencies of the quad-core intel? xeon? processor 5400 series including flexible motherboard guidelines (fmb) (see section 2.13.1 ). refer to the appropriate platform design guidelines for implementation details. the quad-core intel? xeon? processor 5400 series supports either 1066 mhz, 1333 mhz, or 1600 mhz front side bus operat ions. the fsb utilizes a split-transaction, deferred reply protocol and source-synchronous transfer (sst) of address and data to improve performance. the processor transfer s data four times per bus clock (4x data transfer rate, as in agp 4x). along with the 4x data bus, the address bus can deliver addresses two times per bus clock and is referred to as a ?double-clocked? or a 2x address bus. in addition, the request phase completes in one clock cycle. the fsb is also used to deliver interrupts. signals on the fsb use assisted gunning transceiver logic (agtl+) level voltages. section 2.1 contains the electrical specifications of the fsb while implementation details are fully described in the appropriat e platform design guidelines (refer to section 1.3 ). 1.1 terminology a ?#? symbol after a signal name refers to an active low signal, indicating a signal is in the asserted state when driven to a low level. for example, when reset# is low, a reset has been requested. conversely, when nmi is high, a nonmaskable interrupt has occurred. in the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ?#? symbol implies that the signal is inverted. for example, d[3:0] = ?hlhl? refers to a hex ?a?, and d[3:0]# = ?lhlh? also refers to a hex ?a? (h= high logic level, l= low logic level). table 1-1. quad-core intel? xeon? processor 5400 series # of processor cores l1 cache l2 advanced cache front side bus frequency package 4 32 kb instruction per core 32 kb data per core 2x6 mb shared 1600 mhz 1333 mhz 1066 mhz fc-lga 771 lands
11 commonly used terms are explained here for clarification: ? quad-core intel? xeon? processor 5400 series - intel 64-bit microprocessor intended for dual processor servers and workstations based on intel?s 45 nanometer process, in the pc-lga 771 pack age with four processor cores. for this document ?processors? is used as the ge neric term for the ?quad-core intel? xeon? processor 5400 series?. the term ?processors? and ?quad-core intel? xeon? processor 5400 series? are inclusive of quad-core intel? xeon? processor x5482, quad-core intel? xeon? processor x5400 series, quad-core intel? xeon? processor e5400 series, and quad-core intel? xeon? processor l5400 series. ? quad-core intel? xe on? processor x5492 ? an ultra performance version of the quad-core intel? xeon? processor 5400 series. for this document ?quad- core intel? xeon? processor x5492? is used to call out specifications that are unique to the quad-core inte l? xeon? processor x5492 sku. ? quad-core intel? xe on? processor x5482 ? an ultra performance version of the quad-core intel? xeon? processor 5400 series. for this document ?quad- core intel? xeon? processor x5482? is used to call out specifications that are unique to the quad-core intel? xeon? pr ocessor x5482 sku. e-step version of the x5482 falls into the x5400 family specifications ? quad-core intel? xeon? processor x5400 series - an accelerated performance version of the quad-core in tel? xeon? processor x5400 series. for this document ?quad-core intel? xeon? processor x5400 series? is used to call out specifications that are unique to th e quad-core intel? xeon? processor x5400 series sku. ? quad-core intel? xeon? processor e5400 series ? a mainstream performance version of the quad-core in tel? xeon? processor x5400 series. for this document ?quad-core intel? xeon? processor e5400 series? is used to call out specifications that are unique to th e quad-core intel? xeon? processor e5400 series sku. ? quad-core intel? xeon? processor l5400 series - intel 64-bit microprocessor intended for dual processor server blades and embedded servers. the quad-core intel? xeon? processor l5400 series is a lower voltage and lower power version of the quad-core intel? xeon? processor 5400 series. for this document ?quad-core intel? xeon? processor l5400 series? is used to call out specifications that are unique to the quad-core intel? xeon? processor l5400 series sku. ? quad-core intel? xe on? processor l5408 - intel 64-bit microprocessor intended for dual processor server blad es and embedded servers. the quad-core intel? xeon? processor l5408 is a lower voltage and lower power version of the quad-core intel? xeon? processor 5400 series supporting higher case temperatures. it supports a thermal profile with nominal and short-term conditions designed to meet network equipment build ing system (nebs) level 3 compliance. for this document ?quad-core intel? xe on? processor l5408? is used to call out specifications that are unique to the quad-core intel? xeon? processor l5408 sku. ? fc-lga (flip chip land grid array) package ? the quad-core intel? xeon? processor 5400 series package is a land grid array, consisting of a processor core mounted on a pinless substrate with 771 la nds, and includes an integrated heat spreader (ihs). ? lga771 socket ? the quad-core intel? xeon? processor 5400 series interfaces to the baseboard through this surface mount, 771 land socket. see the lga771 socket design guidelines for details regarding this socket.
12 ? processor core ? processor core with integrated l1 cache. l2 cache and system bus interface are shared between the two core s on the die. all ac timing and signal integrity specifications are at the pads of the system bus interface. ? front side bus (fsb) ? the electrical interface that connects the processor to the chipset. also referred to as the proce ssor system bus or the system bus. all memory and i/o transactions, as well as interrupt messages, pass between the processor and chipset over the fsb. ? dual independent bus (dib) ? a front side bus architecture with one processor on each of several processor buses, rather than a processor bus shared between two processor agents. the dib architectu re provides improved performance by allowing increased fsb speeds and bandwidth. ? flexible motherboard guidelines (fmb) ? estimate of the maximum values the quad-core intel? xeon? processor 5400 series will have over certain time periods. actual specifications for future processors may differ. ? functional operation ? refers to the normal operating conditions in which all processor specifications, including dc, ac , fsb, signal quality, mechanical and thermal are satisfied. ? storage conditions ? refers to a non-operational state. the processor may be installed in a platform, in a tray, or loose. processors may be sealed in packaging or exposed to free air. under these conditions, processor lands should not be connected to any supply voltages, have any i/os biased or receive any clocks. upon exposure to ?free air? (that is, unse aled packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (msl) as indi cated on the packaging material. ? priority agent ? the priority agent is the host bridge to the processor and is typically known as the chipset. ? symmetric agent ? a symmetric agent is a processor which shares the same i/o subsystem and memory array, and runs the same operating system as another processor in a system. systems using symmetric agents are known as symmetric multiprocessing (smp) systems. ? integrated heat spreader (ihs) ? a component of the processor package used to enhance the thermal performance of the package. component thermal solutions interface with the processor at the ihs surface. ? thermal design power (tdp) ? processor thermal solutions should be designed to meet this target. it is the highest expected sustainable power while running known power intensive applications. td p is not the maximum power that the processor can dissipate. ? intel ? 64 architecture ? an enhancement to intel's ia-32 architecture that allows the processor to execute operating systems and applications written to take advantage of the 64-bit extension technology. ? enhanced intel speedstep ? technology ? technology that provides power management capabilities to servers and workstations. ? platform environment control interface (peci) ? a proprietary one-wire bus interface that provides a communication channel between intel processor and external thermal monitoring devices, for use in fan speed control. peci communicates readings from the processor?s digital thermometer. peci replaces the thermal diode available in previous processors. ? intel ? virtualization technology ? processor virtualization, which when used in conjunction with virtual machine monitor software enables multiple, robust independent software environments inside a single platform.
13 ? vrm (voltage regulator module) ? dc-dc converter built onto a module that interfaces with a card edge socket and supplies the correct voltage and current to the processor based on the logic state of the processor vid bits. ? evrd (enterprise voltage regulator down) ? dc-dc converter integrated onto the system board that provides the correct voltage and current to the processor based on the logic state of the processor vid bits. ? v cc ? the processor core power supply. ? v ss ? the processor ground. ? v tt ? fsb termination voltage. 1.2 state of data the data contained within this document is the most accurate information available by the publication date of this document. 1.3 references material and concepts available in the fo llowing documents may be beneficial when reading this document: notes: 1. contact your intel representative for the latest revision of these documents 2. document is available publicly at http://developer.intel.com . document document number 1 notes ap-485, intel ? processor identification and the cpuid instruction 241618 2 intel ? 64 and ia-32 architectures software developer?s manual, volume 1 intel ? 64 and ia-32 architectures softwa re developer?s manual, volume 2a intel ? 64 and ia-32 architectures softwa re developer?s manual, volume 2b intel ? 64 and ia-32 architectures softwa re developer?s manual, volume 3a intel ? 64 and ia-32 architectures softwa re developer?s manual, volume 3b 253665 253666 253667 253668 253669 2 intel ? 64 and ia-32 intel ? architectures optimization reference manual 248966 2 intel ? 64 and ia-32 intel ? architectures software developer's manual documentation changes 252046 2 quad-core intel? xeon? processo r 5400 series specification update 318585 2 voltage regulator module (vrm) and enterprise voltage regulator-down (evrd) 11.0 design guidelines 315889 2 quad-core intel? xeon? processor 5400 series thermal/mechanical design guidelines (tmdg) 318611 1 lga771 socket mechanical design guide 313871 2 quad-core intel? xeon? processor 5400 series boundary scan descriptive language (bsdl) model 318587 2
14
15 quad-core intel? xeon? processor 540 0 series electrical specifications 2 quad-core intel? xeon? processor 5400 series electrical specifications 2.1 front side bus and gtlref most quad-core intel? xeon? processor 5400 series fsb signals use assisted gunning transceiver logic (agtl+) signalin g technology. this technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. agtl+ buffers are open-drain and require pull-up resistors to provide the high logic level and termination. agtl+ output buffers differ from gtl+ buffers with the addition of an active pmos pull-up transistor to ?assist? the pull-up resistors during the first clock of a low-to-high voltage transition. platforms implement a termination voltage level for agtl+ signals defined as v tt . because platforms implement separate power planes for each processor (and chipset), separate v cc and v tt supplies are necessary. this configuration allows for improved noise tolerance as processor frequency increases. speed enhancements to data and address buses have made signal integrity considerations and platform design methods even more critical than with previous processor families. design guidelines for the processor fsb are detailed in the appropriate platform design guidelines (refer to section 1.3 ). the agtl+ inputs require reference voltages (gtlref_data_mid, gtlref_data_end, gtlref_add_mid, and gtlref_add_end) which are used by the receivers to determine if a signal is a logical 0 or a logical 1. gtlref_data_mid and gtlref_data_end is used for the 4x front side bus signaling group and gtlref_add_mid and gtlref_add_end is used for the 2x and common clock front side bus signaling groups. gtlref_data_mid, gtlref_data_end, gtlref_add_mid, and gtlref_add_end must be generated on the baseboard (see ta b l e 2 - 1 9 for gtlref_data_mid, gtlref_data_end, gtlref_add_mid, and gtlref_add_end specifications). refer to th e applicable platform design guidelines for details. termination resistors (r tt ) for agtl+ signals are provided on the processor silicon and are terminated to v tt . the on-die termination resistors are always enabled on the quad-core intel? xeon? processor 54 00 series to control reflections on the transmission line. intel chipsets also provid e on-die termination, thus eliminating the need to terminate the bus on the baseboard for most agtl+ signals. some fsb signals do not include on-die termination (r tt ) and must be terminated on the baseboard. see ta b l e 2 - 8 for details regarding these signals. the agtl+ bus depends on incident wave swit ching. therefore, timing calculations for agtl+ signals are based on flight time as opposed to capacitive deratings. analog signal simulation of the fsb, including tr ace lengths, is highly recommended when designing a system. contact your intel field representative to obtain the quad-core intel? xeon? processor 5400 series signal in tegrity models, which includes buffer and package models.
quad-core intel? xeon? processor 540 0 series electrical specifications 16 2.2 power and ground lands for clean on-chip processor core power distribution, the processor has 223 v cc (power) and 267 v ss (ground) inputs. all v cc lands must be connected to the processor power plane, while all v ss lands must be connected to the system ground plane. the processor v cc lands must be supplied with the vo ltage determined by the processor voltage identification (vid) signals. see ta b l e 2 - 3 for vid definitions. twenty two lands are specified as v tt , which provide termination for the fsb and provides power to the i/o buffers. the platfo rm must implement a separate supply for these lands which meets the v tt specifications outlined in ta b l e 2 - 1 2 . 2.3 decoupling guidelines due to its large number of transistors and high internal clock speeds, the quad-core intel? xeon? processor 5400 series is capable of generating large average current swings between low and full power states. this may cause voltages on power planes to sag below their minimum values if bulk deco upling is not adequate. larger bulk storage (c bulk ), such as electrolytic capacitors, supply voltage during longer lasting changes in current demand by the component, such as coming out of an idle condition. similarly, they act as a storage well for current when entering an idle condition from a running condition. care must be taken in the baseboard design to ensure that the voltage provided to the processor remains within the specifications listed in ta b l e 2 - 1 2 . failure to do so can result in timing violations or reduced lifetime of the component. for further information and guidelines, refer to the appropriate platform design guidelines. 2.3.1 v cc decoupling vcc regulator solutions need to provide bulk capacitance with a low effective series resistance (esr), and the baseboard designer must assure a low interconnect resistance from the regulator (evrd or vrm pins) to the lga771 socket. bulk decoupling must be provided on the basebo ard to handle large voltage swings. the power delivery solution must insure the voltage and current specifications are met (as defined in ta b l e 2 - 1 2 ). for further information regarding power delivery, decoupling and layout guidelines, refer to the a ppropriate platform design guidelines . 2.3.2 v tt decoupling bulk decoupling must be prov ided on the baseboard. decoupling solutions must be sized to meet the expected load. to insure optimal performance, various factors associated with the power delivery solution must be considered including regulator type, power plane and trace sizing, and component placement. a conservative decoupling solution consists of a combination of low esr bulk capacitors and high frequency ceramic capacitors. for furthe r information regarding power delivery, decoupling and layout guidelines, refer to th e appropriate platform design guidelines. 2.3.3 front side bu s agtl+ decoupling the quad-core intel? xeon? processor 5400 series integrates signal termination on the die, as well as a portion of the requir ed high frequency decoupling capacitance on the processor package. however, additional high frequency capacitance must be added to the baseboard to properly decouple the return currents from the fsb. bulk decoupling must also be provided by the baseboard for proper agtl+ bus operation. decoupling guidelines are described in the appropriate platform design guidelines.
17 quad-core intel? xeon? processor 540 0 series electrical specifications 2.4 front side bus clock (bclk[1:0]) and processor clocking bclk[1:0] directly controls the fsb interface speed as well as the core frequency of the processor. as in previous processor ge nerations, the quad-core intel? xeon? processor 5400 series core frequency is a multiple of the bclk[1:0] frequency. the processor bus ratio multiplier is set during manufacturing. the default setting is for the maximum speed of the processor. it is possible to override this setting using software (see the intel? 64 and ia-32 architectures software developer?s manual ). this permits operation at lower frequencies than the processor?s tested frequency. the processor core frequency is configured during reset by using values stored internally during manufacturing. the stored value sets the highest bus fraction at which the particular processor can operate. if lower speeds are desired, the appropriate ratio can be configured via the clock_flex_max msr. for details of operation at core frequencies lower than the maximum rated processor speed, refer to the intel? 64 and intel? 64 and ia-32 architectu res software developer?s manual. clock multiplying within the processor is pr ovided by the internal phase locked loop (pll), which requires a constant frequency bc lk[1:0] input, with exceptions for spread spectrum clocking. processor dc specifications for the bclk[1:0] inputs are provided in ta b l e 2 - 2 0 . these specifications must be met while also meeting signal integrity requirements as outlined in ta b l e 2 - 2 0 . the quad-core intel? xeon? processor 5400 series utilizes differential clocks. ta b l e 2 - 1 contains processor core frequency to fsb multipliers and their corresponding core frequencies. notes: 1. individual processors operate only at or below the frequency marked on the package. 2. listed frequencies are not necessarily committed production frequencies. 3. for valid processor core frequencies, see quad-core intel? xeon? processor 5400 series specification update . 4. the lowest bus ratio supported by the quad-c ore intel? xeon? processor 5400 series is 1/6. 2.4.1 front side bus frequenc y select signals (bsel[2:0]) upon power up, the fsb frequency is set to the maximum supported by the individual processor. bsel[2:0] are cmos outputs which must be pulled up to v tt , and are used to select the fsb freque ncy. please refer to ta b l e 2 - 1 5 for dc specifications. ta b l e 2 - 2 defines the possible combinations of the signals and the frequency associated with each combination. the frequency is determined by the processor(s), chipset, and clock synthesizer. all fsb agents must operate at the same core and fsb frequency. see the appropriate platform design guidelines for further details. table 2-1. core frequency to fsb multiplier configuration core frequency to fsb multiplier core frequency with 400.000 mhz bus clock core frequency with 333.333 mhz bus clock core frequency with 266.666 mhz bus clock notes 1/6 2.40 ghz 2 ghz 1.60 ghz 1, 2, 3, 4 1/7 2.80 ghz 2.33 ghz 1.87 ghz 1, 2, 3 1/7.5 3 ghz 2.50 ghz 2 ghz 1, 2, 3 1/8 3.20 ghz 2.66 ghz 2.13 ghz 1, 2, 3 1/8.5 3.40 ghz 2.83 ghz 2.27 ghz 1, 2, 3 1/9 3.60 ghz 3 ghz 2.40 ghz 1, 2, 3 1/9.5 3.80 ghz 3.16 ghz 2.53 ghz 1, 2, 3
quad-core intel? xeon? processor 540 0 series electrical specifications 18 2.4.2 pll power supply an on-die pll filter solution is implemented on the quad-core intel? xeon? processor 5400 series. the v ccpll input is used for this configuration in quad-core intel? xeon? processor 5400 series-based platforms. please refer to ta b l e 2 - 1 2 for dc specifications. refer to the appropriate plat form design guidelines for decoupling and routing guidelines. 2.5 voltage identification (vid) the voltage identification (vid) specif ication for the quad-core intel? xeon? processor 5400 series is defined by the voltage regulator module (vrm) and enterprise voltage regulator-down (evr d) 11.0 design guidelines . the voltage set by the vid signals is the reference vr output voltage to be delivered to th e processor vcc pins. vid signals are open drain outputs, which must be pulled up to v tt . please refer to ta b l e 2 - 1 6 for the dc specifications for these signals. a voltage range is provided in ta b l e 2 - 1 2 and changes with frequency. the specifications have been set such that one voltage regulator can operate with all supported frequencies. individual processor vid values may be calibrated during manufacturing such that two devices at the same core frequency may have different default vid settings. this is reflected by the vid range values provided in ta b l e 2 - 3 . the quad-core intel? xeon? processor 5400 series uses six voltage identification signals, vid[6:1], to support automatic selection of power supply voltages. ta b l e 2 - 3 specifies the voltage level corresponding to the state of vid[6:1]. a ?1? in this table refers to a high voltage level and a ?0? refers to a low voltage level. if the processor socket is empty (vid[6:1] = 111111), or the voltage regulation circuit cannot supply the voltage that is requested, the voltag e regulator must disable itself. see the voltage regulator module (vrm) and enterprise voltage regulator-down (evrd) 11.0 design guidelines for further details. although the voltage regulator module (vrm) and enterprise voltage regulator-down (evrd) 11.0 design guidelines defines vid[7:0], vid7 and vid0 are not used on the quad-core intel? xeon? processor 5400 series; vid7 is always hard wired low at the voltage regulator. table 2-2. bsel[2:0] frequency table bsel2 bsel1 bsel0 bus clock frequency 0 0 0 266.66 mhz 001 reserved 010 reserved 011 reserved 1 0 0 333.33 mhz 101 reserved 1 1 0 400 mhz 111 reserved
19 quad-core intel? xeon? processor 540 0 series electrical specifications the quad-core intel? xeon? processor 5400 series provides the ability to operate while transitioning to an adjacent vid and its associated processor core voltage (v cc ). this will represent a dc shift in the load line. it should be noted that a low-to-high or high-to-low voltage state change may result in as many vid transitions as necessary to reach the target core voltage. transitions above the specified vid are not permitted. ta b l e 2 - 1 2 includes vid step sizes and dc shift ranges. minimum and maximum voltages must be maintained as shown in ta b l e 2 - 1 3 and ta b l e 2 - 2 . the vrm or evrd utilized must be capable of regulating its output to the value defined by the new vid. dc specifications for dynamic vid transitions are included in ta b l e 2 - 1 2 and ta b l e 2 - 1 4 . refer to the voltage regulator module (vrm) and enterprise voltage regulator-down (evrd) 11.0 design guidelines for further details. power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable.
quad-core intel? xeon? processor 540 0 series electrical specifications 20 notes: 1. when the ?111111? vid pattern is observed, th e voltage regulator output should be disabled. 2. shading denotes the expected vid range of the quad-core intel? xeon? processor 5400 series . 3. the vid range includes vid transitions th at may be initiated by thermal events, assertion of the forcepr# signal (see section 6.2.4 ), extended halt state transitions (see section 7.2.2 ), or enhanced intel speedstep ? technology transitions (see section 7.3 ). the extended halt state must be enabled for th e processor to remain within its specifications 4. once the vrm/evrd is operating after power-up, if either the ou tput enable signal is de-asserted or a specific vid off code i s received, the vrm/evrd must turn off its output (the output should go to high impedance) within 500 ms and latch off until power is cycled. refer to voltage regulator module (vrm) and enterprise voltage regulator-down (evrd) 11.0 design guidelines . table 2-3. voltage identification definition hex vid6 vid5 vid4 vid3 vid2 vid1 v cc_max hex vid6 vid5 vid4 vid3 vid2 vid1 v cc_max 7a 1 1 1 1 0 1 0.8500 3c 0 1 1 1 1 0 1.2375 78 1 1 1 1 0 0 0.8625 3a 0 1 1 1 0 1 1.2500 76 1 1 1 0 1 1 0.8750 38 0 1 1 1 0 0 1.2625 74 1 1 1 0 1 0 0.8875 36 0 1 1 0 1 1 1.2750 72 1 1 1 0 0 1 0.9000 34 0 1 1 0 1 0 1.2875 70 1 1 1 0 0 0 0.9125 32 0 1 1 0 0 1 1.3000 6e 1 1 0 1 1 1 0.9250 30 0 1 1 0 0 0 1.3125 6c 1 1 0 1 1 0 0.9375 2e 0 1 0 1 1 1 1.3250 6a 1 1 0 1 0 1 0.9500 2c 0 1 0 1 1 0 1.3375 68 1 1 0 1 0 0 0.9625 2a 0 1 0 1 0 1 1.3500 66 1 1 0 0 1 1 0.9750 28 0 1 0 1 0 0 1.3625 64 1 1 0 0 1 0 0.9875 26 0 1 0 0 1 1 1.3750 62 1 1 0 0 0 1 1.0000 24 0 1 0 0 1 0 1.3875 60 1 1 0 0 0 0 1.0125 22 0 1 0 0 0 1 1.4000 5e 1 0 1 1 1 1 1.0250 20 0 1 0 0 0 0 1.4125 5c 1 0 1 1 1 0 1.0375 1e 0 0 1 1 1 1 1.4250 5a 1 0 1 1 0 1 1.0500 1c 0 0 1 1 1 0 1.4375 58 1 0 1 1 0 0 1.0625 1a 0 0 1 1 0 1 1.4500 56 1 0 1 0 1 1 1.0750 18 0 0 1 1 0 0 1.4625 54 1 0 1 0 1 0 1.0875 16 0 0 1 0 1 1 1.4750 52 1 0 1 0 0 1 1.1000 14 0 0 1 0 1 0 1.4875 50 1 0 1 0 0 0 1.1125 12 0 0 1 0 0 1 1.5000 4e 1 0 0 1 1 1 1.1250 10 0 0 1 0 0 0 1.5125 4c 1 0 0 1 1 0 1.1375 0e 0 0 0 1 1 1 1.5250 4a 1 0 0 1 0 1 1.1500 0c 0 0 0 1 1 0 1.5375 48 1 0 0 1 0 0 1.1625 0a 0 0 0 1 0 1 1.5500 46 1 0 0 0 1 1 1.1750 08 0 0 0 1 0 0 1.5625 44 1 0 0 0 1 0 1.1875 06 0 0 0 0 1 1 1.5750 42 1 0 0 0 0 1 1.2000 04 0 0 0 0 1 0 1.5875 40 1 0 0 0 0 0 1.2125 02 0 0 0 0 0 1 1.6000 3e 0 1 1 1 1 1 1.2250 00 0 0 0 0 0 0 off 1
21 quad-core intel? xeon? processor 540 0 series electrical specifications note: the ll_id[1:0] signals are used to select the correct loadline slope for the processor. note: the ms_id[1:0] signals are provided to indicate the market segment for the processor and may be used for future processor co mpatibility or for keying. 2.6 reserved, unused, and test signals all reserved signals must remain unconnected. connection of these signals to v cc , v tt , v ss , or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. see chapter 4 for a land listing of the processor and the location of all reserved signals. for reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. unused active high inputs should be connected through a resistor to ground (v ss ). unused outputs can be left unconnected; however, this may interfere with some tap functions, comp licate debug probing, and prevent boundary scan testing. a resistor must be used when tying bidirectional signals to power or ground. when tying any signal to power or ground, a resistor will also allow for system testability. resistor values should be with in 20% of the impedance of the baseboard trace for fsb signals, unless otherwise no ted in the appropriate platform design guidelines. for unused agtl+ input or i/o signals, use pull-up resistors of the same value as the on-die termination resistors (r tt ). for details see ta b l e 2 - 1 9 . tap, cmos asynchronous inputs, and cmos asynchronous outputs do not include on- die termination. inputs and utilized output s must be terminated on the baseboard. unused outputs may be terminated on the baseboard or left unconnected. note that leaving unused outputs unterminated may interfere with some tap functions, complicate debug probing, and prevent boundary scan testing. signal termination for these signal types is discussed in the appropriate platform design guidelines. the testhi signals must be tied to the processor v tt using a matched resistor, where a matched resistor has a resistance value within 20% of the impedance of the board transmission line traces. for example, if the trace impedance is 50 , then a value between 40 and 60 is required. table 2-4. loadline selection truth table for ll_id[1:0] ll_id1 ll_id0 description 00reserved 01dual-core intel ? xeon ? processor 5100 series, dual-core intel? xeon? processor 5200 series, and quad-core intel? xeon? processor 5400 series 10reserved 11quad-core intel ? xeon ? processor 5300 series table 2-5. market segment select ion truth table for ms_id[1:0] ms_id1 ms_id0 description 0 0 dual-core intel? xeon? processor 5200 series 0 1 dual-core intel? xeon? processor 5100 series 1 0 quad-core intel? xeon? processor 5300 series 1 1 quad-core intel? xeon? processor 5400 series
quad-core intel? xeon? processor 540 0 series electrical specifications 22 the testhi signals must use individual pull-up resistors as detailed below. a matched resistor must be used for each signal: ? testhi10 ? cannot be groupe d with other testhi signals ? testhi11 ? cannot be groupe d with other testhi signals ? testhi12 - cannot be grouped with other testhi signals 2.7 front side bus signal groups the fsb signals have been combined into groups by buffer type. agtl+ input signals have differential input buffers, which use gtlref_data and gtlref_add as reference levels. in this document, the term ?agtl+ input? refers to the agtl+ input group as well as the agtl+ i/o group when receiving. similarly, ?agtl+ output? refers to the agtl+ output group as well as the agtl+ i/o group when driving. agtl+ asynchronous outputs can become active anytime and include an active pmos pull-up transistor to assist during the first clock of a low-to-high voltage transition. with the implementation of a source synchr onous data bus comes the need to specify two sets of timing parameters. one set is for common clock signals whose timings are specified with respect to rising edge of bclk0 (ads#, hit#, hitm#, and so forth) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and addre ss) as well as rising edge of bclk0. asynchronous signals are still present (a20m#, ignne#, and so forth) and can become active at any time during the clock cycle. ta b l e 2 - 6 identifies which signals are common clock, source synchronous and asynchronous. table 2-6. fsb signal groups (sheet 1 of 2) signal group type signals 1 agtl+ common clock input synchronous to bclk[1:0] bpri#, defer#, reset#, rs[2:0]#, rsp#, trdy#; agtl+ common clock output synchronous to bclk[1:0] bpm4#, bpm[2:1]#, bpmb[2:1]# agtl+ common clock i/o synchronous to bclk[1:0] ads#, ap[1:0]#, binit# 2 , bnr# 2 , bpm5#, bpm3#, bpm0#,bpmb3# , bpmb0#, br[1:0]#, dbsy#, dp[3:0]#, drdy#, hit# 2 , hitm# 2 , lock#, mcerr# 2 agtl+ source synchronous i/o synchronous to assoc. strobe agtl+ strobes i/o synchronous to bclk[1:0] adstb[1:0]#, dstbp[3:0]#, dstbn[3:0]# open drain output asynchronous ferr#/pbe#, ierr#, prochot#, thermtrip#, tdo cmos asynchronous input asynchron ous a20m#, forcepr#, ignne#, init#, lint0/intr, lint1/nmi, pwrgood, smi#, stpclk# signals associated strobe req[4:0]#,a[16:3]#, a[37:36]# adstb0# a[35:17]# adstb1# d[15:0]#, dbi0# dstbp0#, dstbn0# d[31:16]#, dbi1# dstbp1#, dstbn1# d[47:32]#, dbi2# dstbp2#, dstbn2# d[63:48]#, dbi3# dstbp3#, dstbn3#
23 quad-core intel? xeon? processor 540 0 series electrical specifications notes: 1. refer to chapter 5 for signal descriptions. 2. these signals may be driven simultane ously by multiple agents (wired-or). ta b l e 2 - 7 outlines the signals which include on-die termination (r tt ). ta b l e 2 - 8 outlines non agtl+ signals including open drain signals. ta b l e 2 - 9 provides signal reference voltages. notes: 1. these signals have rtt in the package with a 80 pullup to v tt . 2. these signals have rtt in the package with a 50 pullup to v tt . cmos asynchronous output asynchronous bsel[2:0], vid[6:1] fsb clock clock bclk[1:0] tap input synchronous to tck tck, tdi, tms, trst# tap output synchronous to tck tdo power/other power/other comp[3:0], gtlref_add_mid, gtlref_add_end, gtlref_data_mid, gtlref_data_end, ll_id[1:0], ms_id[1:0], peci, reserved, sktocc#, testin1, testin2, testhi[12:10], v cc , vcc_die_sense, vcc_die_sense2, vccpll, vid_select, vss_die_sense, vss_die_sense2, v ss , v tt , vtt_out, vtt_sel table 2-6. fsb signal groups (sheet 2 of 2) signal group type signals 1 table 2-7. agtl+ signal description table agtl+ signals with r tt agtl+ signals with no r tt a[37:3]#, ads#, adstb[1: 0]#, ap[1:0]#, binit#, bnr#, bpri#, d[63:0]#, dbi[3:0]#, dbsy#, defer#, dp[3:0]#, drdy#, dstbn[3:0]#, dstbp[3:0]#, hit#, hitm#, lock#, mcerr#, req[4:0]#, rs[2:0]#, rsp#, trdy# bpm[5:0]#,bpmb[3:0]#, reset#, br[1:0]# table 2-8. non agtl+ signal description table signals with r tt signals with no r tt forcepr# 1 , prochot# 2 a20m#, bclk[1:0], bsel[2:0], comp[3:0], ferr#/pbe#, gtlref_add_mid, gtlref_add_end, gtlref_data_mid, gtlref_data_end, ierr#, ignne#, init#, lint0/intr, lint1/nmi, ll_id[1:0], ms_id[1:0], peci, pwrgood, sktocc#, smi#, stpclk#, tck, tdi, tdo, testhi[12:8], thermtrip#, tms, trdy#, trst#, vcc_die_sense, vcc_die_sense2, vid[6:1], vid_select, vss_die_sense, vss_die_sense2, vtt_sel table 2-9. signal reference voltages gtlref cmos a[37:3]#, ads#, adstb[1: 0]#, ap[1:0]#, binit#, bnr#, bpm[5:0]#, bpmb[3:0]#, bpri#, br[1:0]#, d[63:0]#, dbi[3:0]#, dbsy#, defer#, dp[3:0]#, drdy#, dstbn[3:0]#, dstbp[3:0]#, forcepr#, hit#, hitm#, lock#, mcerr#, reset#, req[4:0]#, rs[2:0]#, rsp#, trdy# a20m#, lint0/intr, lint1/nmi, ignne#, init#, pwrgood, smi#, stpclk#, tck, tdi, tms, trst#
quad-core intel? xeon? processor 540 0 series electrical specifications 24 2.8 cmos asynchronous and open drain asynchronous signals legacy input signals such as a20m#, ignne#, init#, smi# , and stpclk# utilize cmos input buffers. legacy output signal s such as ferr#/pbe#, ierr#, prochot#, and thermtrip# utilize open drain output bu ffers. all of the cmos and open drain signals are required to be asserted/deasserted for at least eight bclks in order for the processor to recognize the proper signal state. see section 2.13 for the dc specifications. see chapter 6 for additional timing requirements for entering and leaving the low power states. 2.9 test access port (tap) connection due to the voltage levels supported by othe r components in the test access port (tap) logic, it is recommended that the processor(s) be first in the tap chain followed by any other components within the system. a translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltag e. similar considerations must be made for tck, tdo, tms, and trst#. two copies of each signal may be required with each driving a different voltage level. 2.10 platform environmental control interface (peci) dc specifications peci is an intel proprietary one-wire interface that provides a communication channel between intel processors and chipset comp onents to external thermal monitoring devices. the quad-core intel? xeon? proce ssor 5400 series contains digital thermal sensor (dts) sprinkled both inside and outside the cores in a die. these sensors are implemented as analog-to-digital converters calibrated at the factory for reasonable accuracy to provide a digital representation of relative processor temperature. peci provides an interface to relay the highest dts temperature within a die to external devices for thermal/fan speed control. more detailed information may be found in the platform environment control interface (peci) specification. 2.10.1 dc characteristics the peci interface operates at a nominal voltage set by v tt . the set of dc electrical specifications shown in ta b l e 2 - 1 0 is used with devices normally operating from a v tt interface supply. v tt nominal levels will vary between processor families. all peci devices will operate at the v tt level determined by the processor installed in the system. for specific nominal v tt levels, refer to the appropriate processor emts.
25 quad-core intel? xeon? processor 540 0 series electrical specifications note: 1. v tt supplies the peci interface. peci behavior does not affect v tt min/max specifications. 2. the leakage specification applies to powered devices on the peci bus. 3. one node is counted for each client and one node for the system host. extended trace lengths might appear as additional nodes. 2.10.2 input device hysteresis the input buffers in both client and host models must use a schmitt-triggered input design for improved noise immunity. use figure 2-1 as a guide for input buffer design. table 2-10. peci dc electrical limits symbol definition and conditions min max units notes 1 v in input voltage range -0.150 v tt v v hysteresis hysteresis 0.1 * v tt n/a v v n negative-edge threshold voltage 0.275 * v tt 0.500 * v tt v v p positive-edge threshold voltage 0.550 * v tt 0.725 * v tt v i source high level output source (v oh = 0.75 * v tt ) -6.0 n/a ma i sink low level output sink (v ol = 0.25 * v tt ) 0.5 1.0 ma i leak+ high impedance state leakage to v tt (v leak = v ol ) n/a 50 a 2 i leak- high impedance leakage to gnd (v leak = v oh ) n/a 10 a 2 c bus bus capacitance per node n/a 10 pf 3 v noise signal noise immunity above 300 mhz 0.1 * v tt n/a v p-p figure 2-1. input device hysteresis minimum v p maximum v p minimum v n maximum v n peci high range peci low range valid input signal range minimum hysteresis v tt peci ground
quad-core intel? xeon? processor 540 0 series electrical specifications 26 2.11 mixing processors intel supports and validates dual proce ssor configurations only in which both processors operate with the same fsb frequency, core frequency, power segments, and have the same internal cache sizes. mixing components operating at different internal clock frequencies is not supported and will not be validated by intel. combining processors from different power segments is also not supported. note: processors within a system must operate at the same frequency per bits [12:8] of the clock_flex_max msr; however this does no t apply to frequency transitions initiated due to thermal events, extended halt, enhanced intel speedstep technology transitions, or assertion of the forcepr# signal (see chapter 6 ). not all operating systems can support dual pr ocessors with mixed frequencies. mixing processors of different steppings but the same model (as per cpuid instruction) is supported. details regarding the cpui d instruction are provided in the ap-485 intel ? processor identification and the cpuid instruction application note. 2.12 absolute maximum and minimum ratings ta b l e 2 - 1 1 specifies absolute maximum and minimum ratings only, which lie outside the functional limits of the processor. only within specified operation limits, can functionality and long-term reliability be expected. at conditions outside functional operatio n condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. if a device is returned to condit ions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to condit ions exceeding the functional operation condition limits. at conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function or its reliability will be severely degraded. although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields.
27 quad-core intel? xeon? processor 540 0 series electrical specifications notes: 1. for functional operation, all processor electrical, sign al quality, mechanical and thermal specifications must be satisfied. 2. overshoot and undershoot voltage guidelines for input, output, and i/o signals are outlined in chapter 3 . excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor. 3. storage temperature is applicable to storage conditions on ly. in this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias. storag e within these limits will not affect the long-term reliability of the devi ce. for functional operation, plea se refer to the processor case temperature specifications. 4. this rating applies to the processor and does not include any tray or packaging. 5. failure to adhere to this specification can affect the long-term reliability of the processor. 2.13 processor dc specifications the processor dc specifications in this section are defined at the processor die (pads) unless noted otherwise. see chapter 4 for the quad-core intel? xeon? processor 5400 series land listings and chapter 5 for signal definitions. voltage and current specifications are detailed in ta b l e 2 - 1 2 . for platform planning refer to ta b l e 2 - 1 3 and ta b l e 2 - 1 4 , which provides v cc static and transient tolerances. this same information is presented graphically in figure 2-8 and figure 2-4 . the fsb clock signal group is detailed in ta b l e 2 - 2 0 . bsel[2:0] and vid[6:1] signals are specified in ta b l e 2 - 1 5 . the dc specifications for the agtl+ signals are listed in ta b l e 2 - 1 6 . legacy signals and test access port (tap) signals follow dc specifications similar to gtl+. the dc specifications fo r the pwrgood input and tap signal group are listed in ta b l e 2 - 1 6 . ta b l e 2 - 1 2 through ta b l e 2 - 1 8 list the dc specifications for the processor and are valid only while meeting specifications for case temperature (t case as specified in chapter 6, ?thermal specifications? ), clock frequency, and input volt ages. care should be taken to read all notes associated with each parameter. 2.13.1 flexible motherbo ard guidelines (fmb) the flexible motherboard (fmb) guidelines are estimates of the maximum values the quad-core intel? xeon? processor 5400 series will have over certain time periods. the values are only estimates and actual spec ifications for future processors may differ. processors may or may not have specifications equal to the fmb value in the foreseeable future. system designers should meet the fmb values to ensure their systems will be compatible with future quad-core intel? xeon? processor 5400 series. table 2-11. processor ab solute maximum ratings symbol parameter min max unit notes 1, 2 v cc core voltage with respect to v ss -0.30 1.35 v v tt fsb termination voltage with respect to v ss -0.30 1.45 v t case processor case temperature see chapter 6 see chapter 6 c t storage storage temperature -40 85 c3, 4, 5
quad-core intel? xeon? processor 540 0 series electrical specifications 28 table 2-12. voltage and current sp ecifications (sheet 1 of 2) symbol parameter min typ max unit notes 1, 11 vid vid range 0.850 1.3500 v v cc v cc for processor core launch - fmb see ta b l e 2 - 1 3 and ta b l e 2 - 1 4 ; figure 2-7 , figure 2-8 , figure 2-9 , figure 2-10 v 2, 3, 4, 6, 9 v cc_boot default vcc voltage for initial power up 1.10 v 2 v vid_step vid step size during a transition 12.5 mv v vid_shift total allowable dc load line shift from vid steps 450 mv 10 v tt fsb termination voltage (dc + ac specification) 1.045 1.10 1.155 v 8,13 v ccpll pll supply voltage (dc + ac specification) 1.455 1.500 1.605 v 12 i cc i cc for quad-core intel? xeon? processor x5482 with multiple vid launch - fmb 150 a 4,5,6,9,18 i cc i cc for quad-core intel? xeon? processor x5400 series with multiple vid launch - fmb 125 a 4,5,6,9 i cc i cc for quad-core intel? xeon? processor e5400 series with multiple vid launch - fmb 102 a 4, 5, 6, 9 i cc i cc for quad-core intel? xeon? processor l5400 series with multiple vid launch - fmb 60 a 4,5,6,9 i cc i cc for quad-core intel? xeon? processor l5408 with multiple vid launch - fmb 48 a 4,5,6,9 i cc_reset i cc_reset for quad-core intel? xeon? processor x5482 with multiple vid launch - fmb 150 a 17,18 i cc_reset i cc_reset for quad-core intel? xeon? processor x5400 series with multiple vid launch - fmb 125 a 17 i cc_reset i cc_reset for quad-core intel? xeon? processor e5400 series with multiple vid launch - fmb 102 a 17 i cc_reset i cc_reset for quad-core intel? xeon? processor l5400 series with multiple vid launch - fmb 60 a 17 i cc_reset i cc_reset for quad-core intel? xeon? processor l5408 with multiple vid launch - fmb 48 a 17
29 quad-core intel? xeon? processor 540 0 series electrical specifications notes: 1. unless otherwise noted, all specifications in this table are based on final silic on characterization data. 2. these voltages are targets only. a variable voltage source should exist on systems in the event that a different voltage is required. see section 2.5 for more information. i tt i cc for v tt supply before v cc stable i cc for v tt supply after v cc stable 8 7 a15 i cc_tdc thermal design current (tdc) quad-core intel? xeon? processor x5482 launch - fmb 130 a 6,14,18 i cc_tdc thermal design current (tdc) quad-core intel? xeon? processor x5400 series launch - fmb 110 a 6,14 i cc_tdc thermal design current (tdc) quad-core intel? xeon? processor e5400 series launch - fmb 80 a 6,14 i cc_tdc thermal design current (tdc) quad-core intel? xeon? processor l5400 series launch - fmb 50 a 6,14 i cc_tdc thermal design current (tdc) quad-core intel? xeon? processor l5408 launch - fmb 40 a 6,14 i cc_vtt_out dc current that may be drawn from v tt_out per land 580 ma 16 i cc_gtlref i cc for gtlref_data_mid, gtlref_data_end, gtlref_add_mid, and gtlref_add_end 200 a 7 i cc_vccpll i cc for pll supply 260 ma 12 i tcc i cc for quad-core intel? xeon? processor x5482 during active thermal control circuit (tcc) 150 a 18 i tcc i cc for quad-core intel? xeon? processor x5400 series during active thermal control circuit (tcc) 125 a i tcc i cc for quad-core intel? xeon? processor e5400 series during active thermal control circuit (tcc) 102 a i tcc i cc for quad-core intel? xeon? processor l5400 series during active thermal control circuit (tcc) 60 a i tcc i cc for quad-core intel? xeon? processor l5408 during active thermal control circuit (tcc) 48 a table 2-12. voltage and current sp ecifications (sheet 2 of 2) symbol parameter min typ max unit notes 1, 11
quad-core intel? xeon? processor 540 0 series electrical specifications 30 3. the voltage specification requirements are meas ured across the vcc_die_sense and vss_die_sense lands and across the vcc_die_sense2 and vss_die_se nse2 lands with an osci lloscope set to 100 mhz bandwidth, 1.5 pf maximum probe capacitance, and 1 m minimum impedance. the maximum length of ground wire on the probe should be less than 5 mm. ensure external noise from the system is not coupled in the scope probe. 4. the processor must not be subjected to any static v cc level that exceeds the v cc_max associated with any particular current. failure to adhere to this specification can shorten processor lifetime. 5. i cc_max specification is based on maximum v cc loadline. refer to figure 2-7 , figure 2-8 , figure 2-9 and figure 2-10 for details. the processor is capable of drawing i cc_max for up to 10 ms. refer to figure 2-1 for further details on the average processor current draw over various time durations. 6. fmb is the flexible motherboard guideline. these guidelines are for estimation purposes only. see section 2.13.1 for further details on fmb guidelines. 7. this specification represents the total cu rrent for gtlref_data_mi d, gtlref_data_end, gtlref_add_mid, and gtlref_add_end. 8. v tt must be provided via a separate voltage source and must not be connected to v cc . this specification is measured at the land. 9. minimum v cc and maximum i cc are specified at the maximum processor case temperature (tcase) shown in figure 6-2 and figure 6-3 . 10. this specification refers to the total reduction of th e load line due to vid tran sitions below the specified vid. 11. individual processor vid values may be calibrated du ring manufacturing such that two devices at the same frequency may have different vid settings. 12. this specification appl ies to the vccpll land. 13. baseboard bandwidth is limited to 20 mhz. 14. i cc_tdc is the sustained (dc equivalent) current that the processor is capable of drawing indefinitely and should be used for the voltage regu lator temperature assessment. the voltage regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion. please see the applicable design guidelines for further de tails. the processor is capable of drawing i cc_tdc indefinitely. refer to figure 2-1 for further details on the average processor current draw over various time durations. this parameter is based on design characterization and is not tested. 15. this is the maximum total current drawn from the v tt plane by only one processor with r tt enabled. this specification does not include the current coming from on-board termination (r tt ), through the signal line. refer to the appropriate platform design guide and th e voltage regulator design guidelines to determine the total i tt drawn by the system. this parameter is based on design characterization and is not tested. 16. i cc _ vtt _ out is specified at 1.1 v. 17. i cc_reset is specified while pwrgood and reset# are asserted. 18. the quad-core intel? xeon? processor x5482 is in tended for dual processor workstations only. . notes: 1. processor or voltage regulator thermal protection circ uitry should not trip for load currents greater than i cc_tdc . 2. not 100% tested. specified by design characterization. figure 2-2. quad-core intel? xeon? proc essor x5482 load current versus time 12 0 12 5 13 0 13 5 14 0 14 5 15 0 15 5 16 0 0.01 0.1 1 10 100 1000 time duration (s) sustained current (a)
31 quad-core intel? xeon? processor 540 0 series electrical specifications notes: 1. processor or voltage regulator thermal protection circuitry should not trip for load currents greater than i cc_tdc . 2. not 100% tested. specified by design characterization. notes: 1. processor or voltage regulator thermal protection circuitry should not trip for load currents greater than i cc_tdc . 2. not 100% tested. specified by design characterization. figure 2-3. quad-core intel? xeon? processor x5400 series load current versus time 10 0 10 5 110 115 12 0 12 5 13 0 0.01 0.1 1 10 100 1000 time duration (s) sustained current (a) figure 2-4. quad-core intel? xeon? processor e5400 series load current versus time 75 80 85 90 95 10 0 10 5 0.01 0.1 1 10 100 1000 time duration (s) sustained current (a)
quad-core intel? xeon? processor 540 0 series electrical specifications 32 notes: 1. processor or voltage regulator thermal protection circ uitry should not trip for load currents greater than i cc_tdc . 2. not 100% tested. specified by design characterization. figure 2-5. quad-core intel? xeon? processor l5400 series load current versus time 40 45 50 55 60 65 70 0.01 0.1 1 10 100 1000 time duration (s) sustained current (a) table 2-13. quad-core intel? xeon? processor x5482 v cc static and transient toleranc e (sheet 1 of 2) i cc (a) v cc_max (v) v cc_typ (v) v cc_min (v) notes 0 vid - 0.000 vid - 0.010 vid - 0.020 1,2,3 5 vid - 0.006 vid - 0.016 vid - 0.026 1,2,3 10 vid - 0.013 vid - 0.023 vid - 0.033 1,2,3 15 vid - 0.019 vid - 0.029 vid - 0.039 1,2,3 20 vid - 0.025 vid - 0.035 vid - 0.045 1,2,3 25 vid - 0.031 vid - 0.041 vid - 0.051 1,2,3 30 vid - 0.038 vid - 0.048 vid - 0.058 1,2,3 35 vid - 0.044 vid - 0.054 vid - 0.064 1,2,3 40 vid - 0.050 vid - 0.060 vid - 0.070 1,2,3 45 vid - 0.056 vid - 0.066 vid - 0.076 1,2,3 50 vid - 0.063 vid - 0.073 vid - 0.083 1,2,3 55 vid - 0.069 vid - 0.079 vid - 0.089 1,2,3 60 vid - 0.075 vid - 0.085 vid - 0.095 1,2,3 65 vid - 0.081 vid - 0.091 vid - 0.101 1,2,3 70 vid - 0.087 vid - 0.097 vid - 0.108 1,2,3 75 vid - 0.094 vid - 0.104 vid - 0.114 1,2,3 80 vid - 0.100 vid - 0.110 vid - 0.120 1,2,3 85 vid - 0.106 vid - 0.116 vid - 0.126 1,2,3 90 vid - 0.113 vid - 0.123 vid - 0.133 1,2,3 95 vid - 0.119 vid - 0.129 vid - 0.139 1,2,3 100 vid - 0.125 vid - 0.135 vid - 0.145 1,2,3 105 vid - 0.131 vid - 0.141 vid - 0.151 1,2,3 110 vid - 0.138 vid - 0.148 vid - 0.158 1,2,3 115 vid - 0.144 vid - 0.154 vid - 0.164 1,2,3
33 quad-core intel? xeon? processor 540 0 series electrical specifications notes: 1. the v cc_min and v cc_max loadlines represent static and transient limits. please see section 2.13.2 for v cc overshoot specifications. 2. this table is intended to ai d in reading discrete points on figure 2-7 . 3. the loadlines specify voltage limits at the die meas ured at the vcc_die_sense and vss_die_sense lands and across the vcc_die_sense2 and vss_die_sense2 lands. voltage regulation feedback for voltage regulator circuits must also be taken from pr ocessor vcc_die_sense and vss_die_sense lands and vcc_die_sense2 and vss_die_sense2 lands. refer to the voltage regulator module (vrm) and enterprise voltage regulator down (evrd) 11.0 design guidelines for socket load line guidelines and vr implementation. please refer to the appropriate platfo rm design guide for details on vr implementation. 120 vid - 0.150 vid - 0.160 vid - 0.170 1,2,3 125 vid - 0.156 vid - 0.166 vid - 0.176 1,2,3 130 vid - 0.163 vid - 0.173 vid - 0.183 1,2,3 135 vid - 0.169 vid - 0.179 vid - 0.189 1,2,3 140 vid - 0.175 vid - 0.185 vid - 0.195 1,2,3 145 vid - 0.181 vid - 0.191 vid - 0.201 1,2,3 150 vid - 0.188 vid - 0.198 vid - 0.208 1,2,3 table 2-13. quad-core intel? xeon? processor x5482 v cc static and transient tolerance (sheet 2 of 2) i cc (a) v cc_max (v) v cc_typ (v) v cc_min (v) notes table 2-14. quad-core intel? xeon? processor x5400 series, quad-core intel? xeon? processor e5400 series, quad-core intel? xeon? processor l5400 series v cc static and transient tolerance (sheet 1 of 2) i cc (a) v cc_max (v) v cc_typ (v) v cc_min (v) notes 0 vid - 0.000 vid - 0.015 vid - 0.030 1, 2, 3 5 vid - 0.006 vid - 0.021 vid - 0.036 1, 2, 3 10 vid - 0.013 vid - 0.028 vid - 0.043 1, 2, 3 15 vid - 0.019 vid - 0.034 vid - 0.049 1, 2, 3 20 vid - 0.025 vid - 0.040 vid - 0.055 1, 2, 3 25 vid - 0.031 vid - 0.046 vid - 0.061 1, 2, 3 30 vid - 0.038 vid - 0.053 vid - 0.068 1, 2, 3 35 vid - 0.044 vid - 0.059 vid - 0.074 1, 2, 3 40 vid - 0.050 vid - 0.065 vid - 0.080 1, 2, 3 45 vid - 0.056 vid - 0.071 vid - 0.086 1, 2, 3 50 vid - 0.063 vid - 0.077 vid - 0.093 1, 2, 3, 6 55 vid - 0.069 vid - 0.084 vid - 0.099 1, 2, 3, 6 60 vid - 0.075 vid - 0.090 vid - 0.105 1, 2, 3, 6 65 vid - 0.081 vid - 0.096 vid - 0.111 1, 2, 3, 5 , 6 70 vid - 0.087 vid - 0.103 vid - 0.118 1, 2, 3, 5 , 6 75 vid - 0.094 vid - 0.109 vid - 0.124 1, 2, 3, 5 , 6 80 vid - 0.100 vid - 0.115 vid - 0.130 1, 2, 3, 5 , 6 85 vid - 0.106 vid - 0.121 vid - 0.136 1, 2, 3, 5 , 6 90 vid - 0.113 vid - 0.128 vid - 0.143 1, 2, 3, 5 , 6 95 vid - 0.119 vid - 0.134 vid - 0.149 1, 2, 3, 5 , 6 100 vid - 0.125 vid - 0.140 vid - 0.155 1, 2, 3, 5 , 6 105 vid - 0.131 vid - 0.146 vid - 0.161 1, 2, 3, 4 , 5 , 6
quad-core intel? xeon? processor 540 0 series electrical specifications 34 notes: 1. the v cc_min and v cc_max loadlines represent static an d transient limits. please see section 2.13.2 for v cc overshoot specifications. 2. this table is intended to ai d in reading discrete points on figure 2-8 and figure 2-9 . 3. the loadlines specify voltage limits at the die meas ured at the vcc_die_sense and vss_die_sense lands and across the vcc_die_sense2 and vss_die_sense2 lands. voltage regulati on feedback for voltage regulator circuits must also be taken from processor vcc_die_sense and vss_die_sense lands and vcc_die_sense2 and vss_die_sense2 lands. refer to the voltage regulator module (vrm) and enterprise voltage regulator down (evrd) 11.0 design guidelines for socket load line guidelines and vr implementation. please refer to the appropriate plat form design guide for details on vr implementation. 4. i cc values greater than 102a are not applicable for the quad-core intel? xeon? processor e5400 series. 5. i cc values greater than 60a are not applicable for the quad-core intel? xeon? processor l5400 series. 6. i cc values greater than 48a are not applicable for the quad-core intel? xeon? processor l5408. 110 vid - 0.138 vid - 0.153 vid - 0.168 1, 2, 3, 4 , 5 , 6 115 vid - 0.144 vid - 0.159 vid - 0.174 1, 2, 3, 4 , 5 , 6 120 vid - 0.150 vid - 0.165 vid - 0.180 1, 2, 3, 4 , 5 , 6 125 vid - 0.156 vid - 0.171 vid - 0.186 1, 2, 3, 4 , 5 , 6 table 2-14. quad-core intel? xeon? processor x5400 series, quad-core intel? xeon? processor e5400 series, quad-core intel? xeon? processor l5400 series v cc static and transient tolerance (sheet 2 of 2) i cc (a) v cc_max (v) v cc_typ (v) v cc_min (v) notes figure 2-6. v cc static and transient tolerance load lines vid - 0.000 vid - 0.010 vid - 0.020 vid - 0.030 vid - 0.040 vid - 0.050 vid - 0.060 vid - 0.070 vid - 0.080 vid - 0.090 vid - 0.100 0 5 10 15 20 25 30 35 40 45 50 icc [a] vcc [v] vcc maximum v cc typical vcc minimum vid - 0.000 vid - 0.010 vid - 0.020 vid - 0.030 vid - 0.040 vid - 0.050 vid - 0.060 vid - 0.070 vid - 0.080 vid - 0.090 vid - 0.100 0 5 10 15 20 25 30 35 40 45 50 icc [a] vcc [v] vcc maximum v cc typical vcc minimum
35 quad-core intel? xeon? processor 540 0 series electrical specifications figure 2-7. quad-core intel? xeon? processor x5482 v cc static and transient tolerance load lines vid - 0.000 vid - 0.050 vid - 0.100 vid - 0.150 vid - 0.200 vid - 0.250 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 icc [a] vcc [v] v cc maximum v cc ty pic al v cc minimum
quad-core intel? xeon? processor 540 0 series electrical specifications 36 figure 2-8. quad-core intel? xe on? processor x5400 series v cc static and transient tolerance load lines figure 2-9. quad-core intel? xe on? processor e5400 series v cc static and transient tolerance load lines vid - 0.000 vid - 0.020 vid - 0.040 vid - 0.060 vid - 0.080 vid - 0.100 vid - 0.120 vid - 0.140 vid - 0.160 vid - 0.180 vid - 0.200 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 icc [a] vcc [v] v cc maximum v cc typical v cc minimum vid - 0.000 vid - 0.020 vid - 0.040 vid - 0.060 vid - 0.080 vid - 0.100 vid - 0.120 vid - 0.140 vid - 0.160 vid - 0.180 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 icc [a] vcc [v] v cc maximum v cc ty pical v cc minimum
37 quad-core intel? xeon? processor 540 0 series electrical specifications notes: 1. the v cc_min and v cc_max loadlines represent static and transient limits. please see section 2.13.2 for vcc overshoot specifications. 2. refer to ta b l e 2 - 1 2 for processor vid information. 3. refer to ta b l e 2 - 1 3 for v cc static and transient tolerance 4. the load lines specify voltage limits at the die measured at the vcc_die_sense and vss_die_sense lands and the vcc_die_sense2 and vss_die_sense2 lands. voltage regulation feedback for voltage regulator circuits must also be taken from pr ocessor vcc_die_sense and vss_die_sense lands and vcc_die_sense2 and vss_die_sense2 lands. refer to the voltage regulator module (vrm) and enterprise voltage regulator down (evrd) 11.0 design guidelines for socket load line guidelines and vr implementation. please refer to the appropriate platfo rm design guide for details on vr implementation. notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. v il is defined as the maximum voltage level at a receiv ing agent that will be inte rpreted as a logical low value. 3. v ih is defined as the minimum voltage level at a receiv ing agent that will be inte rpreted as a logical high value. 4. v ih and v oh may experience excursions above v tt . however, input signal drivers must comply with the signal quality specifications. 5. this is the pull down driver resistance. refer to processor i/o buffer models for i/v characteristics. measured at 0.31*v tt . r on (min) = 0.158*r tt . r on (typ) = 0.167*r tt . r on (max) = 0.175*r tt . 6. gtlref should be generated from v tt with a 1% tolerance resistor divider. the v tt referred to in these specifications is the instantaneous v tt . 7. specified when on-die r tt and r on are turned off. v in between 0 and v tt . figure 2-10. quad-core intel? xeon? processor l5400 series vcc static and transient tolerance load lines vid - 0.000 vid - 0.020 vid - 0.040 vid - 0.060 vid - 0.080 vid - 0.100 vid - 0.120 0 5 10 15 20 25 30 35 40 45 50 55 60 icc [a] vcc [v] v cc maximum v cc ty pic al v cc minimum table 2-15. agtl+ signal group dc specifications symbol parameter min typ max units notes 1 v il input low voltage -0.10 0 gtlref-0.10 v 2,4,6 v ih input high voltage gtlref+0.10 v tt v tt +0.10 v 3,6 v oh output high voltage v tt -0.10 n/a v tt v4,6 r on buffer on resistance 8.25 10.25 12.25 5 i li input leakage current n/a n/a 100 a7
quad-core intel? xeon? processor 540 0 series electrical specifications 38 notes: 1. unless otherwise noted, all specifications in this table apply to a ll processor frequencies. 2. the v tt referred to in these specifications refers to instantaneous v tt . 3. refer to the processor i/o buffer models for i/v characteristics. 4. measured at 0.1*v tt . 5. measured at 0.9*v tt . 6. for vin between 0 v and v tt . measured when the driver is tristated. notes: 1. unless otherwise noted, all specifications in this table apply to a ll processor frequencies. 2. measured at 0.2*v tt . 3. v oh is determined by value of th e external pullup resistor to v tt . refer to platform design guide for details. 4. for v in between 0 v and v oh . 2.13.2 v cc overshoot specification the quad-core intel? xeon? processor 5400 series can tolerate short transient overshoot events where v cc exceeds the vid voltage when transitioning from a high- to-low current load condition. this overshoot cannot exceed vid + v os_max (v os_max is the maximum allowable overshoot above vi d). these specifications apply to the processor die voltage as measured across the vcc_die_sense and vss_die_sense lands and across the vcc_die_sense2 and vss_die_sense2 lands. table 2-16. cmos signal input/output group and tap signal group dc specifications symbol parameter min typ max units notes 1 v il input low voltage -0.10 0.00 0.3 * v tt v2,3 v ih input high voltage 0.7 * v tt v tt v tt + 0.1 v 2 v ol output low voltage -0.10 0 0.1 * v tt v2 v oh output high voltage 0.9 * v tt v tt v tt + 0.1 v 2 i ol output low current 1.70 n/a 4.70 ma 4 i oh output high current 1.70 n/a 4.70 ma 5 i li input leakage current n/a n/a 100 a6 table 2-17. open drain output signal group dc specifications symbol parameter min typ max units notes 1 v ol output low voltage 0 n/a 0.20 * v tt v v oh output high voltage 0.95 * v tt v tt 1.05 * v tt v3 i ol output low current 16 n/a 50 ma 2 i lo leakage current n/a n/a 200 a4 table 2-18. v cc overshoot specifications symbol parameter min max units figure notes v os_max magnitude of v cc overshoot above vid 50 mv 2-11 t os_max time duration of v cc overshoot above vid 25 s 2-11
39 quad-core intel? xeon? processor 540 0 series electrical specifications notes: 1. vos is the measured overshoot voltage. 2. tos is the measured time duration above vid. 2.13.3 die voltage validation core voltage (vcc) overshoot events at the processor must meet the specifications in ta b l e 2 - 1 8 when measured across the vcc_die_sense and vss_die_sense lands and across the vcc_die_sense2 and vss_die_ sense2 lands. overshoot events that are < 10 ns in duration may be ignored. these measurements of processor die level overshoot should be taken with a 10 0 mhz bandwidth limited oscilloscope. 2.14 agtl+ fsb specifications routing topologies are dependent on the processors supported and the chipset used in the design. please refer to the appropriate platform design guidelines for specific implementation details. in most cases, termination resistors are not required as these are integrated into the processor silicon. see ta b l e 2 - 8 for details on which signals do not include on-die termination. please refer to ta b l e 2 - 1 9 for r tt values. valid high and low levels are determined by the input buffers via comparing with a reference voltage called gtlref_data_mid, gtlref_data_end, gtlref_add_mid, and gtlref_add_end. gtlref_data_mid and gtlref_data_end is the reference voltage for the fsb 4x data signals, gtlref_add_mid, and gtlref_add_end is the reference voltage for the fsb 2x address signals and common clock signals. ta b l e 2 - 1 9 lists the gtlref_data_mid, gtlref _data_end, gtlref_add_mid, and gtlref_add_end specifications. figure 2-11. v cc overshoot example waveform example overshoot waveform 0 5 10 15 20 25 time [us] voltage [v] vid - 0.000 vid + 0.050 v os t os t os : overshoot time above vid v os : overshoot above vid
quad-core intel? xeon? processor 540 0 series electrical specifications 40 the agtl+ reference voltages (gtlref_data_mid, gtlref_data_end, gtlref_add_mid, and gtlref_add_end) must be generated on the baseboard using high precision voltage divider circuits. refer to the appropriate platform design guidelines for implementation details. notes: 1. unless otherwise noted, all specifications in this table apply to a ll processor frequencies. 2. the tolerances for this specification have been stated generically to enable system designer to calculate the minimum values across the range of v tt . 3. gtlref_data_mid, gtlref_data_end, gtlref_add_mid, and gtlref_add_end is generated from v tt on the baseboard by a voltage divider of 1% resistor s. the minimum and maximu m specifications account for this resistor tolerance. refer to the appropriate platform design guidelines for implementation details. the v tt referred to in these specifications is the instantaneous v tt . 4. r tt is the on-die termination resistance measured at v ol of the agtl+ output driver. measured at 0.31*v tt . r tt is connected to v tt on die. refer to processor i/o buffer models for i/v characteristics. 5. comp resistance must be provided on the system bo ard with 1% resistors. se e the applicable platform design guide for implementation details. notes: 1. unless otherwise noted, all specifications in this table apply to a ll processor frequencies. 2. crossing voltage is defined as the instantaneous voltage value when the rising edge of bclk0 is equal to the falling edge of bclk1. 3. v havg is the statistical average of the v h measured by the oscilloscope. 4. overshoot is defined as the absolute value of the maximum voltage. 5. undershoot is defined as the abso lute value of the minimum voltage. 6. ringback margin is defined as the absolute voltag e difference between the maximum rising edge ringback and the maximum fallin g edge ringback. table 2-19. agtl+ bus voltage definitions symbol parameter min typ max units notes 1 gtlref_data_mid, gtlref_data_end data bus reference voltage 0.98 * 0.667 * v tt 0.667 * v tt 1.02*0.667 * v tt v2, 3 gtlref_add_mid, gtlref_add_end address bus reference voltage 0.98 * 0.667 * v tt 0.667 * v tt 1.02*0.667 * v tt v2, 3 r tt termination resistance (pull up) 45 50 55 ? 4 comp comp resistance 49.4 49.9 50.4 ? 5 table 2-20. fsb differential bclk specifications symbol parameter min typ max unit figure notes 1 v l input low voltage -0.150 0.0 0.150 v 2-13 v h input high voltage 0.660 0.710 0.850 v 2-13 v cross(abs) absolute crossing point 0.250 0.350 0.550 v 2-13, 2-14 2,9 v cross(rel) relative crossing point 0.250 + 0.5 * (v havg - 0.700) n/a 0.550 + 0.5 * (v havg - 0.700) v 2-13, 2-14 3,8,9,11 vcross range of crossing points n/a n/a 0.140 v 2-13, 2-14 v os overshoot n/a n/a 1.150 v 2-13 4 v us undershoot -0.300 n/a n/a v 2-13 5 v rbm ringback margin 0.200 n/a n/a v 2-13 6 v tr threshold region v cross - 0.100 n/a v cross + 0.100 v 2-13 7 i li input leakage current n/a n/a 100 a10 errefclk-diffrrise errefclk-diff-fall differential rising and falling edge rates 0.6 4 v/ns 2-15 12
41 quad-core intel? xeon? processor 540 0 series electrical specifications 7. threshold region is defined as a region entered aroun d the crossing point voltag e in which the differential receiver switches. it includes input threshold hysteresis. 8. the crossing point must meet the absolute and rela tive crossing point specif ications simultaneously. 9. v havg can be measured directly using ?vtop? on agilent and ?high? on tektronix o scilloscopes. 10. for v in between 0 v and v h . 11. v cross is defined as the total variation of all crossing voltages as defined in note 3. 12. measured from -200 mv to +200 mv on the different ial waveform (derived from refclk+ minus refclk-). the signal must be monotonic through the measur ement region for rise and fall time. the 400 mv measurement window is centered on the differential zero crossing. see figure 2-15 . figure 2-12. electrical test circuit figure 2-13. differential clock waveform vtt 55 ohms, 160 ps/in, 600 mils 0.3nh 0.9nh 0.6nh rtt = 55 ohms 1.3pf 0.2pf ac timings specified at this point (@ buffer pad) vtt buffer long package r load crossing voltage threshold region vh vl overshoot undershoot ringback margin rising edge ringback falling edge ringback, bclk0 bclk1 crossing voltage tp tp = t1: bclk[1:0] period
quad-core intel? xeon? processor 540 0 series electrical specifications 42 figure 2-14. differential cloc k crosspoint specification figure 2-15. differential risi ng and falling edge rates 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 200 250 300 350 400 450 500 550 600 650 vhavg (mv) crossing point (mv) 550 mv 250 mv 250 + 0.5 (vhavg - 700) 550 + 0.5 (vhavg - 700)
43 mechanical specifications 3 mechanical specifications the quad-core intel? xeon? processor 5400 series is packaged in a flip chip land grid array (fc-lga) package that interfaces to the baseboard via a lga771 socket. the package consists of a processor core mounted on a pinless substrate with 771 lands. an integrated heat spreader (ihs) is attach ed to the package substrate and core and serves as the interface for processor component thermal solutions such as a heatsink. figure 3-1 shows a sketch of the processor package components and how they are assembled together. refer to the lga771 socket design guidelines for complete details on the lga771 socket. the package components shown in figure 3-1 include the following: ? integrated heat spreader (ihs) ? thermal interface material (tim) ? processor core (die) ? package substrate ? landside capacitors ?package lands note: this drawing is not to scale and is for reference only. 3.1 package mechanical drawings the package mechanical drawings are shown in figure 3-2 through figure 3-4 . the drawings include dimensions necessary to design a thermal solution for the processor including: ? package reference and tolerance dimensions (total height, length, width, and so forth) ? ihs parallelism and tilt ? land dimensions ? top-side and back-side component keepout dimensions ? reference datums note: all drawing dimensions are in mm [in.]. figure 3-1. processor pa ckage assembly sketch ihs substrate lga771 socket system board capacitors core (die) tim package lands ihs substrate lga771 socket system board capacitors core (die) tim package lands
mechanical specifications 44 note: guidelines on potential ihs flatne ss variation with socket load plate actuation and installation of the cooling solution are available in the processor therma l/mechanical desi gn guidelines. figure 3-2. quad-core intel? xeon? pr ocessor 5400 series package drawing (sheet 1 of 3)
45 mechanical specifications figure 3-3. quad-core intel? xeon? pr ocessor 5400 series package drawing (sheet 2 of 3)
mechanical specifications 46 note: the optional dimple packing marking highlighted by detail f from the above drawing may only be found on initial processors. figure 3-4. quad-core intel? xeon? pr ocessor 5400 series package drawing (sheet 3 of 3)
47 mechanical specifications 3.2 processor component keepout zones the processor may contain components on the substrate that define component keepout zone requirements. decoupling capacitors are typically mounted to either the topside or landside of the package substrate. see figure 3-4 for keepout zones. 3.3 package loading specifications ta b l e 3 - 1 provides dynamic and static load spec ifications for the processor package. these mechanical load limits should not be exceeded during heatsink assembly, mechanical stress testing or standard drop and shipping conditions. the heatsink attach solutions must not include continuous stress onto the processor with the exception of a uniform load to maintain th e heatsink-to-processor thermal interface. also, any mechanical system or component te sting should not exceed these limits. the processor package substrate should not be used as a mechanical reference or load- bearing surface for thermal or mechanical solutions. notes: 1. these specifications apply to uniform compressive loading in a direction perp endicular to the ihs top surface. 2. this is the minimum and maximum st atic force that can be applied by the heatsink and retention solution to maintain the heatsink and processor interface. 3. these specifications are based on limited testing fo r design characterization. loading limits are for the lga771 socket. 4. dynamic compressive load ap plies to all board thickness. 5. dynamic loading is defined as an 11 ms duration average load superimpos ed on the static load requirement. 6. test condition used a heatsink mass of 1 lbm with 50 g acceleration measured at heatsink mass. the dynamic portion of this specification in the product application can have fl exibility in specific values, but the ultimate product of mass times acceleration should not exceed this dynamic load. 7. transient bend is defined as the transient board deflection during manufacturing such as board assembly and system integration. it is a relatively slow bending event compared to shock and vibration tests. 8. for more information on the tr ansient bend limits, please refer to the mas document titled manufacturing with intel ? components using 771-land lga package that interfaces with the mo therboard via a lga771 socket. 9. refer to the quad-core intel? xeon? processor 5400 series thermal/mechanical design guidelines (tmdg) for information on heatsink clip load metrology. table 3-1. package loading specifications parameter board thickness min max unit notes static compressive load 1.57 mm 0.062? 80 18 311 70 n lbf 1,2,3,9 2.16 mm 0.085? 111 25 311 70 n lbf 2.54 mm 0.100? 133 30 311 70 n lbf dynamic compressive load na na 311 n (max static compressive load) + 222 n dynamic loading 70 lbf (max static compressive load) + 50 lbf dynamic loading n lbf 1,3,4,5,6 transient bend limits 1.57 mm 0.062? na 750 me 1,3,7,8
mechanical specifications 48 3.4 package handling guidelines ta b l e 3 - 2 includes a list of guidelines on a pa ckage handling in terms of recommended maximum loading on the processor ihs relati ve to a fixed substrate. these package handling loads may be experien ced during heatsink removal. notes: 1. a shear load is defined as a load applied to th e ihs in a direction parallel to the ihs top surface. 2. a tensile load is defined as a pu lling load applied to the ihs in a direction normal to the ihs surface. 3. a torque load is defined as a twisti ng load applied to the ihs in an ax is of rotation normal to the ihs top surface. 4. these guidelines are based on limited testing for design characterization and incidental applications (one time only). 5. handling guidelines are for the package only and do not include the limits of the processor socket. 3.5 package insertion specifications the quad-core intel? xeon? processor 5400 series can be inserted and removed 15 times from an lga771 socket, which meets the criteria outlined in the lga771 socket design guidelines . 3.6 processor mass specifications the typical mass of the quad-core intel? xeon? processor 5400 series is 21.5 grams [0.76 oz.]. this includes all components which make up the entire processor product. 3.7 processor materials the quad-core intel? xeon? processor 5400 series is assembled from several components. the basic material properties are described in ta b l e 3 - 3 . 3.8 processor markings figure 3-5 shows the topside markings on the processor. this diagram aids in the identification of the quad-core intel? xeon? processor 5400 series. table 3-2. package handling guidelines parameter maximum recommended units notes shear 311 70 n lbf 1,4,5 tensile 111 25 n lbf 2,4,5 torque 3.95 35 n-m lbf-in 3,4,5 table 3-3. processor materials component material integrated heat spreader (ihs) nickel over copper substrate fiber-reinforced resin substrate lands gold over nickel
49 mechanical specifications note: 2d matrix is required for engineerin g samples only (encoded with atpo-s/n). 3.9 processor land coordinates figure 3-6 and figure 3-7 show the top and bottom view of the processor land coordinates, respectively. the coordinates are referred to throughout the document to identify processor lands. figure 3-5. processor top- side markings (example) atpo s/n atpo s/n group1line1 group1line2 group1line3 group1line4 group1line5 atpo s/n legend: group1line1 group1line2 group1line3 group1line4 group1line5 mark text (production mark): 3200dp/12m/1600 intel ? xeon ? proc# sxxx coo i (m) ? ?07 fpo figure 3-6. processor land coordinates, top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak al am an a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak al am an 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 socket 771 quadrants top view v cc / v ss v tt / clocks data address / common clock / async
mechanical specifications 50 figure 3-7. processor land coordinates, bottom view v tt / clocks 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak al am an a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak al am an 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930 socket 771 quadrants bottom view v cc / v ss data address / common clock / async
51 land listing 4 land listing 4.1 quad-core intel? xeon? processor 5400 series pin assignments this section provides sorted land list in ta b l e 4 - 1 and ta b l e 4 - 2 . ta b l e 4 - 1 is a listing of all processor lands ordered alphabetically by land name. ta b l e 4 - 2 is a listing of all processor lands ordered by land number. 4.1.1 land listing by land name table 4-1. land listing by land name (sheet 1 of 20) pin name pin no. signal buffer type direction a03# m5 source sync input/output a04# p6 source sync input/output a05# l5 source sync input/output a06# l4 source sync input/output a07# m4 source sync input/output a08# r4 source sync input/output a09# t5 source sync input/output a10# u6 source sync input/output a11# t4 source sync input/output a12# u5 source sync input/output a13# u4 source sync input/output a14# v5 source sync input/output a15# v4 source sync input/output a16# w5 source sync input/output a17# ab6 source sync input/output a18# w6 source sync input/output a19# y6 source sync input/output a20# y4 source sync input/output a20m# k3 cmos async input a21# aa4 source sync input/output a22# ad6 source sync input/output a23# aa5 source sync input/output a24# ab5 source sync input/output a25# ac5 source sync input/output a26# ab4 source sync input/output a27# af5 source sync input/output a28# af4 source sync input/output a29# ag6 source sync input/output a30# ag4 source sync input/output a31# ag5 source sync input/output a32# ah4 source sync input/output a33# ah5 source sync input/output a34# aj5 source sync input/output a35# aj6 source sync input/output a36# n4 source sync input/output a37# p5 source sync input/output ads# d2 common clk input/output adstb0# r6 source sync input/output adstb1# ad5 source sync input/output ap0# u2 common clk input/output ap1# u3 common clk input/output bclk0 f28 clk input bclk1 g28 clk input binit# ad3 common clk input/output bnr# c2 common clk input/output bpm0# aj2 common clk input/output bpm1# aj1 common clk output bpm2# ad2 common clk output bpm3# ag2 common clk input/output bpm4# af2 common clk output bpm5# ag3 common clk input/output bpmb0# g1 common clk input/output bpmb1# c9 common clk output bpmb2# g4 common clk output bpmb3# g3 common clk input/output bpri# g8 common clk input br0# f3 common clk input/output br1# h5 common clk input table 4-1. land listing by land name (sheet 2 of 20) pin name pin no. signal buffer type direction
land listing 52 bsel0 g29 cmos async output bsel1 h30 cmos async output bsel2 g30 cmos async output comp0 a13 power/other input comp1 t1 power/other input comp2 g2 power/other input comp3 r1 power/other input d00# b4 source sync input/output d01# c5 source sync input/output d02# a4 source sync input/output d03# c6 source sync input/output d04# a5 source sync input/output d05# b6 source sync input/output d06# b7 source sync input/output d07# a7 source sync input/output d08# a10 source sync input/output d09# a11 source sync input/output d10# b10 source sync input/output d11# c11 source sync input/output d12# d8 source sync input/output d13# b12 source sync input/output d14# c12 source sync input/output d15# d11 source sync input/output d16# g9 source sync input/output d17# f8 source sync input/output d18# f9 source sync input/output d19# e9 source sync input/output d20# d7 source sync input/output d21# e10 source sync input/output d22# d10 source sync input/output d23# f11 source sync input/output d24# f12 source sync input/output d25# d13 source sync input/output d26# e13 source sync input/output d27# g13 source sync input/output d28# f14 source sync input/output d29# g14 source sync input/output d30# f15 source sync input/output d31# g15 source sync input/output d32# g16 source sync input/output table 4-1. land listing by land name (sheet 3 of 20) pin name pin no. signal buffer type direction d33# e15 source sync input/output d34# e16 source sync input/output d35# g18 source sync input/output d36# g17 source sync input/output d37# f17 source sync input/output d38# f18 source sync input/output d39# e18 source sync input/output d40# e19 source sync input/output d41# f20 source sync input/output d42# e21 source sync input/output d43# f21 source sync input/output d44# g21 source sync input/output d45# e22 source sync input/output d46# d22 source sync input/output d47# g22 source sync input/output d48# d20 source sync input/output d49# d17 source sync input/output d50# a14 source sync input/output d51# c15 source sync input/output d52# c14 source sync input/output d53# b15 source sync input/output d54# c18 source sync input/output d55# b16 source sync input/output d56# a17 source sync input/output d57# b18 source sync input/output d58# c21 source sync input/output d59# b21 source sync input/output d60# b19 source sync input/output d61# a19 source sync input/output d62# a22 source sync input/output d63# b22 source sync input/output dbi0# a8 source sync input/output dbi1# g11 source sync input/output dbi2# d19 source sync input/output dbi3# c20 source sync input/output dbr# ac2 power/other output dbsy# b2 common clk input/output defer# g7 common clk input dp0# j16 common clk input/output dp1# h15 common clk input/output table 4-1. land listing by land name (sheet 4 of 20) pin name pin no. signal buffer type direction
53 land listing dp2# h16 common clk input/output dp3# j17 common clk input/output drdy# c1 common clk input/output dstbn0# c8 source sync input/output dstbn1# g12 source sync input/output dstbn2# g20 source sync input/output dstbn3# a16 source sync input/output dstbp0# b9 source sync input/output dstbp1# e12 source sync input/output dstbp2# g19 source sync input/output dstbp3# c17 source sync input/output ferr#/pbe# r3 open drain output forcepr# ak6 cmos async input gtlref_add_end g10 power/other input gtlref_add_mid f2 power/other input gtlref_data_end h1 power/other input gtlref_data_mid h2 power/other input hit# d4 common clk input/output hitm# e4 common clk input/output ierr# ab2 open drain output ignne# n2 cmos async input init# p3 cmos async input lint0 k1 cmos async input lint1 l1 cmos async input ll_id0 v2 power/other output ll_id1 aa2 power/other output lock# c3 common clk input/output mcerr# ab3 common clk input/output ms_id0 w1 power/other output ms_id1 v1 power/other output peci g5 power/other input/output prochot# al2 open drain output pwrgood n1 cmos async input req0# k4 source sync input/output req1# j5 source sync input/output req2# m6 source sync input/output req3# k6 source sync input/output req4# j6 source sync input/output reserved am6 reserved a20 table 4-1. land listing by land name (sheet 5 of 20) pin name pin no. signal buffer type direction reserved a23 reserved a24 reserved ac4 reserved ae4 reserved ae6 reserved ah2 reserved ah7 reserved aj3 reserved aj7 reserved ak3 reserved am2 reserved an5 reserved an6 reserved b13 reserved b23 reserved c23 reserved d1 reserved d14 reserved d16 reserved e1 reserved e23 reserved e24 reserved e5 reserved e6 reserved e7 reserved e29 reserved f23 reserved f29 reserved f6 reserved g6 reserved j2 reserved j3 reserved n5 reserved t2 reserved y1 reserved y3 reserved al1 reserved ak1 reserved g27 reserved g26 table 4-1. land listing by land name (sheet 6 of 20) pin name pin no. signal buffer type direction
land listing 54 reserved g24 reserved f24 reserved f26 reserved f25 reserved g25 reserved w3 reserved am2 reset# g23 common clk input rs0# b3 common clk input rs1# f5 common clk input rs2# a3 common clk input rsp# h4 common clk input sktocc# ae8 power/other output smi# p2 cmos async input stpclk# m3 cmos async input tck ae1 tap input tdi ad1 tap input tdo af1 tap output testhi10 p1 power/other input testhi11 l2 power/other input testhi12 ae3 power/other input testin1 w2 power/other input testin2 u1 power/other input thermtrip# m2 open drain output tms ac1 tap input trdy# e3 common clk input trst# ag1 tap input vcc aa8 power/other vcc ab8 power/other vcc ac23 power/other vcc ac24 power/other vcc ac25 power/other vcc ac26 power/other vcc ac27 power/other vcc ac28 power/other vcc ac29 power/other vcc ac30 power/other vcc ac8 power/other vcc ad23 power/other vcc ad24 power/other table 4-1. land listing by land name (sheet 7 of 20) pin name pin no. signal buffer type direction vcc ad25 power/other vcc ad26 power/other vcc ad27 power/other vcc ad28 power/other vcc ad29 power/other vcc ad30 power/other vcc ad8 power/other vcc ae11 power/other vcc ae12 power/other vcc ae14 power/other vcc ae15 power/other vcc ae18 power/other vcc ae19 power/other vcc ae21 power/other vcc ae22 power/other vcc ae23 power/other vcc ae9 power/other vcc af11 power/other vcc af12 power/other vcc af14 power/other vcc af15 power/other vcc af18 power/other vcc af19 power/other vcc af21 power/other vcc af22 power/other vcc af8 power/other vcc af9 power/other vcc ag11 power/other vcc ag12 power/other vcc ag14 power/other vcc ag15 power/other vcc ag18 power/other vcc ag19 power/other vcc ag21 power/other vcc ag22 power/other vcc ag25 power/other vcc ag26 power/other vcc ag27 power/other vcc ag28 power/other vcc ag29 power/other table 4-1. land listing by land name (sheet 8 of 20) pin name pin no. signal buffer type direction
55 land listing vcc ag30 power/other vcc ag8 power/other vcc ag9 power/other vcc ah11 power/other vcc ah12 power/other vcc ah14 power/other vcc ah15 power/other vcc ah18 power/other vcc ah19 power/other vcc ah21 power/other vcc ah22 power/other vcc ah25 power/other vcc ah26 power/other vcc ah27 power/other vcc ah28 power/other vcc ah29 power/other vcc ah30 power/other vcc ah8 power/other vcc ah9 power/other vcc aj11 power/other vcc aj12 power/other vcc aj14 power/other vcc aj15 power/other vcc aj18 power/other vcc aj19 power/other vcc aj21 power/other vcc aj22 power/other vcc aj25 power/other vcc aj26 power/other vcc aj8 power/other vcc aj9 power/other vcc ak11 power/other vcc ak12 power/other vcc ak14 power/other vcc ak15 power/other vcc ak18 power/other vcc ak19 power/other vcc ak21 power/other vcc ak22 power/other vcc ak25 power/other table 4-1. land listing by land name (sheet 9 of 20) pin name pin no. signal buffer type direction vcc ak26 power/other vcc ak8 power/other vcc ak9 power/other vcc al11 power/other vcc al12 power/other vcc al14 power/other vcc al15 power/other vcc al18 power/other vcc al19 power/other vcc al21 power/other vcc al22 power/other vcc al25 power/other vcc al26 power/other vcc al29 power/other vcc al30 power/other vcc al9 power/other vcc am11 power/other vcc am12 power/other vcc am14 power/other vcc am15 power/other vcc am18 power/other vcc am19 power/other vcc am21 power/other vcc am22 power/other vcc am25 power/other vcc am26 power/other vcc am29 power/other vcc am30 power/other vcc am8 power/other vcc am9 power/other vcc an11 power/other vcc an12 power/other vcc an14 power/other vcc an15 power/other vcc an18 power/other vcc an19 power/other vcc an21 power/other vcc an22 power/other vcc an25 power/other vcc an26 power/other table 4-1. land listing by land name (sheet 10 of 20) pin name pin no. signal buffer type direction
land listing 56 vcc an8 power/other vcc an9 power/other vcc j10 power/other vcc j11 power/other vcc j12 power/other vcc j13 power/other vcc j14 power/other vcc j15 power/other vcc j18 power/other vcc j19 power/other vcc j20 power/other vcc j21 power/other vcc j22 power/other vcc j23 power/other vcc j24 power/other vcc j25 power/other vcc j26 power/other vcc j27 power/other vcc j28 power/other vcc j29 power/other vcc j30 power/other vcc j8 power/other vcc j9 power/other vcc k23 power/other vcc k24 power/other vcc k25 power/other vcc k26 power/other vcc k27 power/other vcc k28 power/other vcc k29 power/other vcc k30 power/other vcc k8 power/other vcc l8 power/other vcc m23 power/other vcc m24 power/other vcc m25 power/other vcc m26 power/other vcc m27 power/other vcc m28 power/other vcc m29 power/other table 4-1. land listing by land name (sheet 11 of 20) pin name pin no. signal buffer type direction vcc m30 power/other vcc m8 power/other vcc n23 power/other vcc n24 power/other vcc n25 power/other vcc n26 power/other vcc n27 power/other vcc n28 power/other vcc n29 power/other vcc n30 power/other vcc n8 power/other vcc p8 power/other vcc r8 power/other vcc t23 power/other vcc t24 power/other vcc t25 power/other vcc t26 power/other vcc t27 power/other vcc t28 power/other vcc t29 power/other vcc t30 power/other vcc t8 power/other vcc u23 power/other vcc u24 power/other vcc u25 power/other vcc u26 power/other vcc u27 power/other vcc u28 power/other vcc u29 power/other vcc u30 power/other vcc u8 power/other vcc v8 power/other vcc w23 power/other vcc w24 power/other vcc w25 power/other vcc w26 power/other vcc w27 power/other vcc w28 power/other vcc w29 power/other vcc w30 power/other table 4-1. land listing by land name (sheet 12 of 20) pin name pin no. signal buffer type direction
57 land listing vcc w8 power/other vcc y23 power/other vcc y24 power/other vcc y25 power/other vcc y26 power/other vcc y27 power/other vcc y28 power/other vcc y29 power/other vcc y30 power/other vcc y8 power/other vcc_die_sense an3 power/other output vcc_die_sense2 al8 power/other output vccpll d23 power/other input vid_select an7 power/other output vid1 al5 cmos async output vid2 am3 cmos async output vid3 al6 cmos async output vid4 ak4 cmos async output vid5 al4 cmos async output vid6 am5 cmos async output vss a12 power/other vss a15 power/other vss a18 power/other vss a2 power/other vss a21 power/other vss a6 power/other vss a9 power/other vss aa23 power/other vss aa24 power/other vss aa25 power/other vss aa26 power/other vss aa27 power/other vss aa28 power/other vss aa29 power/other vss aa3 power/other vss aa30 power/other vss aa6 power/other vss aa7 power/other vss ab1 power/other vss ab23 power/other table 4-1. land listing by land name (sheet 13 of 20) pin name pin no. signal buffer type direction vss ab24 power/other vss ab25 power/other vss ab26 power/other vss ab27 power/other vss ab28 power/other vss ab29 power/other vss ab30 power/other vss ab7 power/other vss ac3 power/other vss ac6 power/other vss ac7 power/other vss ad4 power/other vss ad7 power/other vss ae10 power/other vss ae13 power/other vss ae16 power/other vss ae17 power/other vss ae2 power/other vss ae20 power/other vss ae24 power/other vss ae25 power/other vss ae26 power/other vss ae27 power/other vss ae28 power/other vss ae29 power/other vss ae30 power/other vss ae5 power/other vss ae7 power/other vss af7 power/other vss af10 power/other vss af13 power/other vss af16 power/other vss af17 power/other vss af20 power/other vss af23 power/other vss af24 power/other vss af25 power/other vss af26 power/other vss af27 power/other vss af28 power/other table 4-1. land listing by land name (sheet 14 of 20) pin name pin no. signal buffer type direction
land listing 58 vss af29 power/other vss af3 power/other vss af30 power/other vss af6 power/other vss ag10 power/other vss ag13 power/other vss ag16 power/other vss ag17 power/other vss ag20 power/other vss ag23 power/other vss ag24 power/other vss ag7 power/other vss ah1 power/other vss ah10 power/other vss ah13 power/other vss ah16 power/other vss ah17 power/other vss ah20 power/other vss ah23 power/other vss ah24 power/other vss ah3 power/other vss ah6 power/other vss aj10 power/other vss aj13 power/other vss aj16 power/other vss aj17 power/other vss aj20 power/other vss aj23 power/other vss aj24 power/other vss aj27 power/other vss aj28 power/other vss aj29 power/other vss aj30 power/other vss aj4 power/other vss ak10 power/other vss ak13 power/other vss ak16 power/other vss ak17 power/other vss ak2 power/other vss ak20 power/other table 4-1. land listing by land name (sheet 15 of 20) pin name pin no. signal buffer type direction vss ak23 power/other vss ak24 power/other vss ak27 power/other vss ak28 power/other vss ak29 power/other vss ak30 power/other vss ak5 power/other vss ak7 power/other vss al10 power/other vss al13 power/other vss al16 power/other vss al17 power/other vss al20 power/other vss al23 power/other vss al24 power/other vss al27 power/other vss al28 power/other vss al3 power/other vss am1 power/other vss am10 power/other vss am13 power/other vss am16 power/other vss am17 power/other vss am20 power/other vss am23 power/other vss am24 power/other vss am27 power/other vss am28 power/other vss am4 power/other vss am7 power/other vss an1 power/other vss an10 power/other vss an13 power/other vss an16 power/other vss an17 power/other vss an2 power/other vss an20 power/other vss an23 power/other vss an24 power/other vss b1 power/other table 4-1. land listing by land name (sheet 16 of 20) pin name pin no. signal buffer type direction
59 land listing vss b11 power/other vss b14 power/other vss b17 power/other vss b20 power/other vss b24 power/other vss b5 power/other vss b8 power/other vss c10 power/other vss c13 power/other vss c16 power/other vss c19 power/other vss c22 power/other vss c24 power/other vss c4 power/other vss c7 power/other vss d12 power/other vss d15 power/other vss d18 power/other vss d21 power/other vss d24 power/other vss d3 power/other vss d5 power/other vss d6 power/other vss d9 power/other vss e11 power/other vss e14 power/other vss e17 power/other vss e2 power/other vss e20 power/other vss e25 power/other vss e26 power/other vss e27 power/other vss e28 power/other vss e8 power/other vss f1 power/other vss f10 power/other vss f13 power/other vss f16 power/other vss f19 power/other vss f22 power/other table 4-1. land listing by land name (sheet 17 of 20) pin name pin no. signal buffer type direction vss f4 power/other vss f7 power/other vss h10 power/other vss h11 power/other vss h12 power/other vss h13 power/other vss h14 power/other vss h17 power/other vss h18 power/other vss h19 power/other vss h20 power/other vss h21 power/other vss h22 power/other vss h23 power/other vss h24 power/other vss h25 power/other vss h26 power/other vss h27 power/other vss h28 power/other vss h29 power/other vss h3 power/other vss h6 power/other vss h7 power/other vss h8 power/other vss h9 power/other vss j4 power/other vss j7 power/other vss k2 power/other vss k5 power/other vss k7 power/other vss l23 power/other vss l24 power/other vss l25 power/other vss l26 power/other vss l27 power/other vss l28 power/other vss l29 power/other vss l3 power/other vss l30 power/other vss l6 power/other table 4-1. land listing by land name (sheet 18 of 20) pin name pin no. signal buffer type direction
land listing 60 vss l7 power/other vss m1 power/other vss m7 power/other vss n3 power/other vss n6 power/other vss n7 power/other vss p23 power/other vss p24 power/other vss p25 power/other vss p26 power/other vss p27 power/other vss p28 power/other vss p29 power/other vss p30 power/other vss p4 power/other vss p7 power/other vss r2 power/other vss r23 power/other vss r24 power/other vss r25 power/other vss r26 power/other vss r27 power/other vss r28 power/other vss r29 power/other vss r30 power/other vss r5 power/other vss r7 power/other vss t3 power/other vss t6 power/other vss t7 power/other vss u7 power/other vss v23 power/other vss v24 power/other vss v25 power/other vss v26 power/other vss v27 power/other vss v28 power/other vss v29 power/other vss v3 power/other vss v30 power/other table 4-1. land listing by land name (sheet 19 of 20) pin name pin no. signal buffer type direction vss v6 power/other vss v7 power/other vss w4 power/other vss w7 power/other vss y2 power/other vss y5 power/other vss y7 power/other vss_die_sense an4 power/other output vss_die_sense2 al7 power/other output vtt a25 power/other vtt a26 power/other vtt b25 power/other vtt b26 power/other vtt b27 power/other vtt b28 power/other vtt b29 power/other vtt b30 power/other vtt c25 power/other vtt c26 power/other vtt c27 power/other vtt c28 power/other vtt c29 power/other vtt c30 power/other vtt d25 power/other vtt d26 power/other vtt d27 power/other vtt d28 power/other vtt d29 power/other vtt d30 power/other vtt e30 power/other vtt f30 power/other vtt_out aa1 power/other output vtt_out j1 power/other output vtt_sel f27 power/other output table 4-1. land listing by land name (sheet 20 of 20) pin name pin no. signal buffer type direction
61 land listing 4.1.2 land listing by land number table 4-2. land listin g by land number (sheet 1 of 20) pin no. pin name signal buffer type direction a10 d08# source sync input/output a11 d09# source sync input/output a12 vss power/other a13 comp0 power/other input a14 d50# source sync input/output a15 vss power/other a16 dstbn3# source sync input/output a17 d56# source sync input/output a18 vss power/other a19 d61# source sync input/output a2 vss power/other a20 reserved a21 vss power/other a22 d62# source sync input/output a23 reserved a24 reserved a25 vtt power/other a26 vtt power/other a3 rs2# common clk input a4 d02# source sync input/output a5 d04# source sync input/output a6 vss power/other a7 d07# source sync input/output a8 dbi0# source sync input/output a9 vss power/other aa1 vtt_out power/other output aa2 ll_id1 power/other output aa23 vss power/other aa24 vss power/other aa25 vss power/other aa26 vss power/other aa27 vss power/other aa28 vss power/other aa29 vss power/other aa3 vss power/other aa30 vss power/other aa4 a21# source sync input/output aa5 a23# source sync input/output aa6 vss power/other aa7 vss power/other aa8 vcc power/other ab1 vss power/other ab2 ierr# open drain output ab23 vss power/other ab24 vss power/other ab25 vss power/other ab26 vss power/other ab27 vss power/other ab28 vss power/other ab29 vss power/other ab3 mcerr# common clk input/output ab30 vss power/other ab4 a26# source sync input/output ab5 a24# source sync input/output ab6 a17# source sync input/output ab7 vss power/other ab8 vcc power/other ac1 tms tap input ac2 dbr# power/other output ac23 vcc power/other ac24 vcc power/other ac25 vcc power/other ac26 vcc power/other ac27 vcc power/other ac28 vcc power/other ac29 vcc power/other ac3 vss power/other ac30 vcc power/other ac4 reserved ac5 a25# source sync input/output ac6 vss power/other ac7 vss power/other ac8 vcc power/other ad1 tdi tap input ad2 bpm2# common clk output ad23 vcc power/other ad24 vcc power/other ad25 vcc power/other table 4-2. land listin g by land number (sheet 2 of 20) pin no. pin name signal buffer type direction
land listing 62 ad26 vcc power/other ad27 vcc power/other ad28 vcc power/other ad29 vcc power/other ad3 binit# common clk input/output ad30 vcc power/other ad4 vss power/other ad5 adstb1# source sync input/output ad6 a22# source sync input/output ad7 vss power/other ad8 vcc power/other ae1 tck tap input ae10 vss power/other ae11 vcc power/other ae12 vcc power/other ae13 vss power/other ae14 vcc power/other ae15 vcc power/other ae16 vss power/other ae17 vss power/other ae18 vcc power/other ae19 vcc power/other ae2 vss power/other ae20 vss power/other ae21 vcc power/other ae22 vcc power/other ae23 vcc power/other ae24 vss power/other ae25 vss power/other ae26 vss power/other ae27 vss power/other ae28 vss power/other ae29 vss power/other ae3 testhi12 power/other input ae30 vss power/other ae4 reserved ae5 vss power/other ae6 reserved ae7 vss power/other ae8 sktocc# power/other output table 4-2. land listing by land number (sheet 3 of 20) pin no. pin name signal buffer type direction ae9 vcc power/other af1 tdo tap output af10 vss power/other af11 vcc power/other af12 vcc power/other af13 vss power/other af14 vcc power/other af15 vcc power/other af16 vss power/other af17 vss power/other af18 vcc power/other af19 vcc power/other af2 bpm4# common clk output af20 vss power/other af21 vcc power/other af22 vcc power/other af23 vss power/other af24 vss power/other af25 vss power/other af26 vss power/other af27 vss power/other af28 vss power/other af29 vss power/other af3 vss power/other af30 vss power/other af4 a28# source sync input/output af5 a27# source sync input/output af6 vss power/other af7 vss power/other af8 vcc power/other af9 vcc power/other ag1 trst# tap input ag10 vss power/other ag11 vcc power/other ag12 vcc power/other ag13 vss power/other ag14 vcc power/other ag15 vcc power/other ag16 vss power/other ag17 vss power/other table 4-2. land listing by land number (sheet 4 of 20) pin no. pin name signal buffer type direction
63 land listing ag18 vcc power/other ag19 vcc power/other ag2 bpm3# common clk input/output ag20 vss power/other ag21 vcc power/other ag22 vcc power/other ag23 vss power/other ag24 vss power/other ag25 vcc power/other ag26 vcc power/other ag27 vcc power/other ag28 vcc power/other ag29 vcc power/other ag3 bpm5# common clk input/output ag30 vcc power/other ag4 a30# source sync input/output ag5 a31# source sync input/output ag6 a29# source sync input/output ag7 vss power/other ag8 vcc power/other ag9 vcc power/other ah1 vss power/other ah10 vss power/other ah11 vcc power/other ah12 vcc power/other ah13 vss power/other ah14 vcc power/other ah15 vcc power/other ah16 vss power/other ah17 vss power/other ah18 vcc power/other ah19 vcc power/other ah2 reserved ah20 vss power/other ah21 vcc power/other ah22 vcc power/other ah23 vss power/other ah24 vss power/other ah25 vcc power/other ah26 vcc power/other table 4-2. land listin g by land number (sheet 5 of 20) pin no. pin name signal buffer type direction ah27 vcc power/other ah28 vcc power/other ah29 vcc power/other ah3 vss power/other ah30 vcc power/other ah4 a32# source sync input/output ah5 a33# source sync input/output ah6 vss power/other ah7 reserved ah8 vcc power/other ah9 vcc power/other aj1 bpm1# common clk output aj10 vss power/other aj11 vcc power/other aj12 vcc power/other aj13 vss power/other aj14 vcc power/other aj15 vcc power/other aj16 vss power/other aj17 vss power/other aj18 vcc power/other aj19 vcc power/other aj2 bpm0# common clk input/output aj20 vss power/other aj21 vcc power/other aj22 vcc power/other aj23 vss power/other aj24 vss power/other aj25 vcc power/other aj26 vcc power/other aj27 vss power/other aj28 vss power/other aj29 vss power/other aj3 reserved aj30 vss power/other aj4 vss power/other aj5 a34# source sync input/output aj6 a35# source sync input/output aj7 reserved aj8 vcc power/other table 4-2. land listin g by land number (sheet 6 of 20) pin no. pin name signal buffer type direction
land listing 64 aj9 vcc power/other ak1 reserved ak10 vss power/other ak11 vcc power/other ak12 vcc power/other ak13 vss power/other ak14 vcc power/other ak15 vcc power/other ak16 vss power/other ak17 vss power/other ak18 vcc power/other ak19 vcc power/other ak2 vss power/other ak20 vss power/other ak21 vcc power/other ak22 vcc power/other ak23 vss power/other ak24 vss power/other ak25 vcc power/other ak26 vcc power/other ak27 vss power/other ak28 vss power/other ak29 vss power/other ak3 reserved ak30 vss power/other ak4 vid4 cmos async output ak5 vss power/other ak6 forcepr# cmos async input ak7 vss power/other ak8 vcc power/other ak9 vcc power/other al1 reserved al10 vss power/other al11 vcc power/other al12 vcc power/other al13 vss power/other al14 vcc power/other al15 vcc power/other al16 vss power/other al17 vss power/other table 4-2. land listing by land number (sheet 7 of 20) pin no. pin name signal buffer type direction al18 vcc power/other al19 vcc power/other al2 prochot# open drain output al20 vss power/other al21 vcc power/other al22 vcc power/other al23 vss power/other al24 vss power/other al25 vcc power/other al26 vcc power/other al27 vss power/other al28 vss power/other al29 vcc power/other al3 vss power/other al30 vcc power/other al4 vid5 cmos async output al5 vid1 cmos async output al6 vid3 cmos async output al7 vss_die_ sense2 power/other al8 vcc_die_ sense2 power/other al9 vcc power/other am1 vss power/other am10 vss power/other am11 vcc power/other am12 vcc power/other am13 vss power/other am14 vcc power/other am15 vcc power/other am16 vss power/other am17 vss power/other am18 vcc power/other am19 vcc power/other am2 reserved am20 vss power/other am21 vcc power/other am22 vcc power/other am23 vss power/other am24 vss power/other am25 vcc power/other table 4-2. land listing by land number (sheet 8 of 20) pin no. pin name signal buffer type direction
65 land listing am26 vcc power/other am27 vss power/other am28 vss power/other am29 vcc power/other am3 vid2 cmos async output am30 vcc power/other am4 vss power/other am5 vid6 cmos async output am6 reserved am7 vss power/other am8 vcc power/other am9 vcc power/other an1 vss power/other an10 vss power/other an11 vcc power/other an12 vcc power/other an13 vss power/other an14 vcc power/other an15 vcc power/other an16 vss power/other an17 vss power/other an18 vcc power/other an19 vcc power/other an2 vss power/other an20 vss power/other an21 vcc power/other an22 vcc power/other an23 vss power/other an24 vss power/other an25 vcc power/other an26 vcc power/other an3 vcc_die_ sense power/other output an4 vss_die_ sense power/other output an5 reserved an6 reserved an7 vid_select power/other output an8 vcc power/other an9 vcc power/other b1 vss power/other table 4-2. land listin g by land number (sheet 9 of 20) pin no. pin name signal buffer type direction b10 d10# source sync input/output b11 vss power/other b12 d13# source sync input/output b13 reserved b14 vss power/other b15 d53# source sync input/output b16 d55# source sync input/output b17 vss power/other b18 d57# source sync input/output b19 d60# source sync input/output b2 dbsy# common clk input/output b20 vss power/other b21 d59# source sync input/output b22 d63# source sync input/output b23 reserved b24 vss power/other b25 vtt power/other b26 vtt power/other b27 vtt power/other b28 vtt power/other b29 vtt power/other b3 rs0# common clk input b30 vtt power/other b4 d00# source sync input/output b5 vss power/other b6 d05# source sync input/output b7 d06# source sync input/output b8 vss power/other b9 dstbp0# source sync input/output c1 drdy# common clk input/output c10 vss power/other c11 d11# source sync input/output c12 d14# source sync input/output c13 vss power/other c14 d52# source sync input/output c15 d51# source sync input/output c16 vss power/other c17 dstbp3# source sync input/output c18 d54# source sync input/output c19 vss power/other table 4-2. land listin g by land number (sheet 10 of 20) pin no. pin name signal buffer type direction
land listing 66 c2 bnr# common clk input/output c20 dbi3# source sync input/output c21 d58# source sync input/output c22 vss power/other c23 reserved c24 vss power/other c25 vtt power/other c26 vtt power/other c27 vtt power/other c28 vtt power/other c29 vtt power/other c3 lock# common clk input/output c30 vtt power/other c4 vss power/other c5 d01# source sync input/output c6 d03# source sync input/output c7 vss power/other c8 dstbn0# source sync input/output c9 bpmb1# common clk output d1 reserved d10 d22# source sync input/output d11 d15# source sync input/output d12 vss power/other d13 d25# source sync input/output d14 reserved d15 vss power/other d16 reserved d17 d49# source sync input/output d18 vss power/other d19 dbi2# source sync input/output d2 ads# common clk input/output d20 d48# source sync input/output d21 vss power/other d22 d46# source sync input/output d23 vccpll power/other input d24 vss power/other d25 vtt power/other d26 vtt power/other d27 vtt power/other d28 vtt power/other table 4-2. land listing by land number (sheet 11 of 20) pin no. pin name signal buffer type direction d29 vtt power/other d3 vss power/other d30 vtt power/other d4 hit# common clk input/output d5 vss power/other d6 vss power/other d7 d20# source sync input/output d8 d12# source sync input/output d9 vss power/other e1 reserved power/other e10 d21# source sync input/output e11 vss power/other e12 dstbp1# source sync input/output e13 d26# source sync input/output e14 vss power/other e15 d33# source sync input/output e16 d34# source sync input/output e17 vss power/other e18 d39# source sync input/output e19 d40# source sync input/output e2 vss power/other e20 vss power/other e21 d42# source sync input/output e22 d45# source sync input/output e23 reserved e24 reserved e25 vss power/other e26 vss power/other e27 vss power/other e28 vss power/other e29 reserved e3 trdy# common clk input e30 vtt power/other e4 hitm# common clk input/output e5 reserved e6 reserved e7 reserved e8 vss power/other e9 d19# source sync input/output f1 vss power/other table 4-2. land listing by land number (sheet 12 of 20) pin no. pin name signal buffer type direction
67 land listing f10 vss power/other f11 d23# source sync input/output f12 d24# source sync input/output f13 vss power/other f14 d28# source sync input/output f15 d30# source sync input/output f16 vss power/other f17 d37# source sync input/output f18 d38# source sync input/output f19 vss power/other f2 gtlref_add_ mid power/other input f20 d41# source sync input/output f21 d43# source sync input/output f22 vss power/other f23 reserved f24 reserved f25 reserved f26 reserved f27 vtt_sel power/other output f28 bclk0 clk input f29 reserved f3 br0# common clk input/output f30 vtt power/other f4 vss power/other f5 rs1# common clk input f6 reserved f7 vss power/other f8 d17# source sync input/output f9 d18# source sync input/output g1 bpmb0# common clk input/output g10 gtlref_add_ end power/other input g11 dbi1# source sync input/output g12 dstbn1# source sync input/output g13 d27# source sync input/output g14 d29# source sync input/output g15 d31# source sync input/output g16 d32# source sync input/output g17 d36# source sync input/output g18 d35# source sync input/output table 4-2. land listin g by land number (sheet 13 of 20) pin no. pin name signal buffer type direction g19 dstbp2# source sync input/output g2 comp2 power/other input g20 dstbn2# source sync input/output g21 d44# source sync input/output g22 d47# source sync input/output g23 reset# common clk input g24 reserved g25 reserved g26 reserved g27 reserved g28 bclk1 clk input g29 bsel0 cmos async output g3 bpmb3# common clk input/output g30 bsel2 cmos async output g4 bpmb2# common clk output g5 peci power/other input/output g6 reserved g7 defer# common clk input g8 bpri# common clk input g9 d16# source sync input/output h1 gtlref_data _end power/other input h10 vss power/other h11 vss power/other h12 vss power/other h13 vss power/other h14 vss power/other h15 dp1# common clk input/output h16 dp2# common clk input/output h17 vss power/other h18 vss power/other h19 vss power/other h2 gtlref_data _mid power/other input h20 vss power/other h21 vss power/other h22 vss power/other h23 vss power/other h24 vss power/other h25 vss power/other h26 vss power/other table 4-2. land listin g by land number (sheet 14 of 20) pin no. pin name signal buffer type direction
land listing 68 h27 vss power/other h28 vss power/other h29 vss power/other h3 vss power/other h30 bsel1 cmos async output h4 rsp# common clk input h5 br1# common clk input h6 vss power/other h7 vss power/other h8 vss power/other h9 vss power/other j1 vtt_out power/other output j10 vcc power/other j11 vcc power/other j12 vcc power/other j13 vcc power/other j14 vcc power/other j15 vcc power/other j16 dp0# common clk input/output j17 dp3# common clk input/output j18 vcc power/other j19 vcc power/other j2 reserved j20 vcc power/other j21 vcc power/other j22 vcc power/other j23 vcc power/other j24 vcc power/other j25 vcc power/other j26 vcc power/other j27 vcc power/other j28 vcc power/other j29 vcc power/other j3 reserved j30 vcc power/other j4 vss power/other j5 req1# source sync input/output j6 req4# source sync input/output j7 vss power/other j8 vcc power/other table 4-2. land listing by land number (sheet 15 of 20) pin no. pin name signal buffer type direction j9 vcc power/other k1 lint0 cmos async input k2 vss power/other k23 vcc power/other k24 vcc power/other k25 vcc power/other k26 vcc power/other k27 vcc power/other k28 vcc power/other k29 vcc power/other k3 a20m# cmos async input k30 vcc power/other k4 req0# source sync input/output k5 vss power/other k6 req3# source sync input/output k7 vss power/other k8 vcc power/other l1 lint1 cmos async input l2 testhi11 power/other input l23 vss power/other l24 vss power/other l25 vss power/other l26 vss power/other l27 vss power/other l28 vss power/other l29 vss power/other l3 vss power/other l30 vss power/other l4 a06# source sync input/output l5 a05# source sync input/output l6 vss power/other l7 vss power/other l8 vcc power/other m1 vss power/other m2 thermtrip# open drain output m23 vcc power/other m24 vcc power/other m25 vcc power/other m26 vcc power/other m27 vcc power/other table 4-2. land listing by land number (sheet 16 of 20) pin no. pin name signal buffer type direction
69 land listing m28 vcc power/other m29 vcc power/other m3 stpclk# cmos async input m30 vcc power/other m4 a07# source sync input/output m5 a03# source sync input/output m6 req2# source sync input/output m7 vss power/other m8 vcc power/other n1 pwrgood power/other input n2 ignne# cmos async input n23 vcc power/other n24 vcc power/other n25 vcc power/other n26 vcc power/other n27 vcc power/other n28 vcc power/other n29 vcc power/other n3 vss power/other n30 vcc power/other n4 a36# source sync input/output n5 reserved n6 vss power/other n7 vss power/other n8 vcc power/other p1 testhi10 power/other input p2 smi# cmos async input p23 vss power/other p24 vss power/other p25 vss power/other p26 vss power/other p27 vss power/other p28 vss power/other p29 vss power/other p3 init# cmos async input p30 vss power/other p4 vss power/other p5 a37# source sync input/output p6 a04# source sync input/output p7 vss power/other table 4-2. land listin g by land number (sheet 17 of 20) pin no. pin name signal buffer type direction p8 vcc power/other r1 comp3 power/other input r2 vss power/other r23 vss power/other r24 vss power/other r25 vss power/other r26 vss power/other r27 vss power/other r28 vss power/other r29 vss power/other r3 ferr#/pbe# open drain output r30 vss power/other r4 a08# source sync input/output r5 vss power/other r6 adstb0# source sync input/output r7 vss power/other r8 vcc power/other t1 comp1 power/other input t2 reserved t23 vcc power/other t24 vcc power/other t25 vcc power/other t26 vcc power/other t27 vcc power/other t28 vcc power/other t29 vcc power/other t3 vss power/other t30 vcc power/other t4 a11# source sync input/output t5 a09# source sync input/output t6 vss power/other t7 vss power/other t8 vcc power/other u1 testin2 power/other input u2 ap0# common clk input/output u23 vcc power/other u24 vcc power/other u25 vcc power/other u26 vcc power/other u27 vcc power/other table 4-2. land listin g by land number (sheet 18 of 20) pin no. pin name signal buffer type direction
land listing 70 u28 vcc power/other u29 vcc power/other u3 ap1# common clk input/output u30 vcc power/other u4 a13# source sync input/output u5 a12# source sync input/output u6 a10# source sync input/output u7 vss power/other u8 vcc power/other v1 ms_id1 power/other output v2 ll_id0 power/other output v23 vss power/other v24 vss power/other v25 vss power/other v26 vss power/other v27 vss power/other v28 vss power/other v29 vss power/other v3 vss power/other v30 vss power/other v4 a15# source sync input/output v5 a14# source sync input/output v6 vss power/other v7 vss power/other v8 vcc power/other w1 ms_id0 power/other output w2 testin1 power/other input w23 vcc power/other w24 vcc power/other w25 vcc power/other w26 vcc power/other w27 vcc power/other w28 vcc power/other w29 vcc power/other w3 reserved w30 vcc power/other w4 vss power/other w5 a16# source sync input/output w6 a18# source sync input/output w7 vss power/other table 4-2. land listing by land number (sheet 19 of 20) pin no. pin name signal buffer type direction w8 vcc power/other y1 reserved y2 vss power/other y23 vcc power/other y24 vcc power/other y25 vcc power/other y26 vcc power/other y27 vcc power/other y28 vcc power/other y29 vcc power/other y3 reserved y30 vcc power/other y4 a20# source sync input/output y5 vss power/other y6 a19# source sync input/output y7 vss power/other y8 vcc power/other table 4-2. land listing by land number (sheet 20 of 20) pin no. pin name signal buffer type direction
71 signal definitions 5 signal definitions 5.1 signal definitions table 5-1. signal definitions (sheet 1 of 8) name type description notes a[37:3]# i/o a[37:3]# (address) define a 2 38 -byte physical memory address space. in sub-phase 1 of the address phase, these signals transmit the address of a transaction. in sub-phase 2, these signals transmit transaction type information. these signals must connect the appropriate pins of all agents on the fsb. a[37:3]# are protected by parity signals ap[1:0]#. a[37:3]# are source synchronous signals and are latched into the rece iving buffers by adstb[1:0]#. on the active-to-inactive transition of reset#, the processors sample a subset of the a[37:3]# lands to determine their power-on configuration. see section 7.1 . 3 a20m# i if a20m# (address-20 mask) is asserted, the processor masks physical address bit 20 (a20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. asserting a20m# emulates the 8086 processor's address wrap- around at the 1 mb boundary. assertion of a20m# is only supported in real mode. a20m# is an asynchronous signal. however, to ensure recognition of this signal following an i/o write instruction, it must be valid along with the trdy# assertion of the corresponding i/o write bus transaction. 2 ads# i/o ads# (address strobe) is assert ed to indicate the validity of the transaction address on the a[37:3]# lands. all bus agents observe the ads# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply id match operations associated with the new transaction. this signal must be connected to the appropriate pins on all quad-core intel? xeon? processor 5400 series fsb agents. 3 adstb[1:0]# i/o address strobes are used to latch a[37:3]# and req[4:0]# on their rising and falling edge. strobes are associated with signals as shown below. 3 ap[1:0]# i/o ap[1:0]# (address parity) are driven by the request initiator along with ads#, a[37:3]#, and the transaction type on the req[4:0]# signals. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. this allows parity to be high when all the covered signals are high. ap[1:0]# must be connected to the appropriate pins of all quad-core intel? xeon? processor 5400 series fsb agents. the following table defines the coverage model of these signals. 3 signals associated strobes req[4:0]#, a[16:3]#, a[37:36]# adstb0# a[35:17]# adstb1# request signals subphase 1 subphase 2 a[37:24]# ap0# ap1# a[23:3]# ap1# ap0# req[4:0]# ap1# ap0#
signal definitions 72 bclk[1:0] i the differential bus clock pair bclk[1:0] (bus clock) determines the fsb frequency. all processor fsb agents must receive these signals to drive their outputs and latch their inputs. all external timing parameters are sp ecified with respect to the rising edge of bclk0 crossing v cross . 3 binit# i/o binit# (bus initialization) may be observed and driven by all processor fsb agents and if used, must connect the appropriate pins of all such agents. if the binit# driver is enabled during power on configuration, binit# is asserted to signal any bus condition that prevents reliable future operation. if binit# observation is enabled during power-on configuration (see section 7.1 ) and binit# is sampled asserted, symmetric agents reset their bus lock# activity and bus request arbitration state machines. the bus agents do not reset their i/o queue (ioq) and transaction tracking state machines upon observation of binit# assertion. once the binit# assertion has been observed, the bus agents will re-arbitrate for the fs b and attempt completion of their bus queue and ioq entries. if binit# observation is disabled during power-on configuration, a priority agent may handle an assertion of binit# as appropriate to the error handling architecture of the system. 3 bnr# i/o bnr# (block next request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. during a bus stall, the current bus owner cannot issue any new transactions. since multiple agents might need to request a bus stall at the same time, bnr# is a wired-or signal which must connect the appropriate pins of all processor fsb agents. in order to avoid wired-or glitches associated with simultaneous edge transitions driven by multiple drivers, bnr# is activated on specific clock edges and sampled on specific clock edges. 3 bpm5# bpm4# bpm3# bpm[2:1]# bpm0# i/o o i/o o i/o bpm[5:0]# (breakpoint monitor) are breakpoint and performance monitor signals. they are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. bpm[5:0]# should connect the appropriate pins of all fsb agents. bpm4# provides prdy# (probe ready) functionality for the tap port. prdy# is a processor output used by debug tools to determine processor debug readiness. bpm5# provides preq# (probe request) functionality for the tap port. preq# is used by debug tools to request debug operation of the processors. bpm[5:4]# must be bussed to all bus agents. please refer to the appropriate platform design guide lines for more detailed information. 2 bpmb3# bpmb[2:1]# bpmb0# i/o o i/o bpmb[3:0]# (breakpoint monitor) are breakpoint and performance monitor signals. they are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. bpmb[3:0]# should connect the appropriate pins of all fsb agents. bpri# i bpri# (bus priority request) is used to arbitrate for ownership of the processor fsb. it must connect the appropriate pins of all processor fsb agents. observing bpri# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. the priority agent keeps bpri# asserted until all of its requests are completed, then releases the bus by deasserting bpri#. 3 br[1:0]# i/o the br[1:0]# signals are sampled on the active-to-inactive transition of reset#. the signal which the agent samples asserted determines its agent id. br0# drives the breq 0# signal in the system and is used by the processor to request the bus. these signals do not have on-die termination and must be terminated. 3 table 5-1. signal definitions (sheet 2 of 8) name type description notes
73 signal definitions bsel[2:0] o the bclk[1:0] frequency select signals bsel[2:0] are used to select the processor input clock frequency. ta b l e 2 - 2 defines the possible combinations of the signals and the frequency associated with each combination. the required freq uency is determined by the processors, chipset, and clock synthesizer. all fsb agents must operate at the same frequency. for more information about these signals, including termination recommendations, refer to the appropriate platform design guideline. comp[3:0] i comp[3:0] must be terminated to vss on the baseboard using precision resistors. these inputs configure the agtl+ drivers of the processor. refer to the appropriate platform design guidelines for implementation details. d[63:0]# i/o d[63:0]# (data) are the data signals. these signals provide a 64-bit data path between the processor fsb agents, and must connect the appropriate pins on all such agents. the data driver asserts drdy# to indicate a valid data transfer. d[63:0]# are quad-pumped signals, and will thus be driven four times in a common cloc k period. d[63:0]# are latched off the falling edge of both dstbp[3:0]# and dstbn[3:0]#. each group of 16 data signals correspond to a pair of one dstbp# and one dstbn#. the following table shows the grouping of data signals to strobes and dbi#. furthermore, the dbi# signals determine the polarity of the data signals. each group of 16 data signals corresponds to one dbi# signal. when the dbi# signal is ac tive, the corresponding data group is inverted and therefore sampled active high. 3 dbi[3:0]# i/o dbi[3:0]# (data bus inversion) are source synchronous and indicate the polarity of the d[63:0]# signals. the dbi[3:0]# signals are activated when the data on the data bus is inverted. if more than half the data bits, within, within a 16-bi t group, would have been asserted electronically low, the bus agent may invert the data bus signals for that particular sub-phase for that 16-bit group. 3 dbr# o dbr# is used only in systems where no debug port connector is implemented on the system board. dbr# is used by a debug port interposer so that an in-target probe can drive system reset. if a debug port connector is implemented in the system, dbr# is a no- connect on the quad-core intel? xeon? processor 5400 series package. dbr# is not a processor signal. dbsy# i/o dbsy# (data bus busy) is asserted by the agent responsible for driving data on the processor fsb to indicate that the data bus is in use. the data bus is released after dbsy# is deasserted. this signal must connect the appropriate pins on all processor fsb agents. 3 table 5-1. signal definitions (sheet 3 of 8) name type description notes data group dstbn#/dst bp# dbi# d[15:0]# 0 0 d[31:16]# 1 1 d[47:32]# 2 2 d[63:48]# 3 3 dbi[3:0] assignment to data bus bus signal data bus signals dbi0# d[15:0]# dbi1# d[31:16]# dbi2# d[47:32]# dbi3# d[63:48]#
signal definitions 74 defer# i defer# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. assertion of defe r# is normally the responsibility of the addressed me mory or i/o agent. this signal must connect the appropriate pins of all processor fsb agents. 3 dp[3:0]# i/o dp[3:0]# (data parity) provide parity protection for the d[63:0]# signals. they are driven by th e agent responsible for driving d[63:0]#, and must connect the appropriate pins of all processor fsb agents. 3 drdy# i/o drdy# (data ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. in a multi-common clock data transfer, drdy# may be deasserted to insert idle clocks. this signal must connect the appropriate pins of all processor fsb agents. 3 dstbn[3:0]# i/o data strobe used to latch in d[63:0]#. 3 dstbp[3:0]# i/o data strobe used to latch in d[63:0]#. 3 ferr#/pbe# o ferr#/pbe# (floating-point error/pending break event) is a multiplexed signal and its meaning is qualified by stpclk#. when stpclk# is not asserted, ferr#/pbe# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error. when stpclk # is not asserted, ferr#/pbe# is similar to the error# signal on the intel387 coprocessor, and is included for compatibility with syst ems using ms-dos*-type floating- point error reporting. when stpclk# is asserted, an assertion of ferr#/pbe# indicates that the processor has a pending break event waiting for service. the assertion of ferr#/pbe# indicates that the processor should be returned to the normal state. for additional information on the pending break event functionality, including the identification of support of the feature and enable/disable information, refer to vol. 3 of the intel ? 64 and ia-32 architectures software developer?s manual and the intel processor identification and the cpuid instruction application note. 2 forcepr# i the forcepr# (force power reduction) input can be used by the platform to cause the quad-core intel? xeon? processor 5400 series to activate the thermal control circuit (tcc). gtlref_add_mid gtlref_add_end i gtlref_add determines the sign al reference level for agtl+ address and common clock input land s. gtlref_add is used by the agtl+ receivers to determine if a signal is a logical 0 or a logical 1. please refer to ta b l e 2 - 1 9 and the appropriate platform design guidelines for ad ditional details. table 5-1. signal definitions (sheet 4 of 8) name type description notes signals associated strobes d[15:0]#, dbi0# dstbn0# d[31:16]#, dbi1# dstbn1# d[47:32]#, dbi2# dstbn2# d[63:48]#, dbi3# dstbn3# signals associated strobes d[15:0]#, dbi0# dstbp0# d[31:16]#, dbi1# dstbp1# d[47:32]#, dbi2# dstbp2# d[63:48]#, dbi3# dstbp3#
75 signal definitions gtlref_data_mid gtlref_data_end i gtlref_data determines the signal reference level for agtl+ data input lands. gtlref_data is us ed by the agtl+ receivers to determine if a signal is a logical 0 or a logical 1. please refer to ta b l e 2 - 1 9 and the appropriate platform design guidelines for additional details. hit# hitm# i/o i/o hit# (snoop hit) and hitm# (hit modified) convey transaction snoop operation results. any fsb agent may assert both hit# and hitm# together to indicate that it requires a snoop stall, which can be continued by reasserting hit# and hitm# together. 3 ierr# o ierr# (internal error) is asserted by a processor as the result of an internal error. assertion of ie rr# is usually accompanied by a shutdown transaction on the processor fsb. this transaction may optionally be converted to an extern al error signal (e.g., nmi) by system core logic. the processor will keep ierr# asserted until the assertion of reset#. this signal does not have on-die termination. 2 ignne# i ignne# (ignore numeric error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating- point instructions. if ignne# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. ignne# has no effect when the ne bit in control register 0 (cr0) is set. ignne# is an asynchronous signal. however, to ensure recognition of this signal following an i/o write instruction, it must be valid along with the trdy# assertion of the corresponding i/o write bus transaction. 2 init# i init# (initialization), when asse rted, resets integer registers inside all processors without affecting their internal caches or floating-point registers. each processor then begins execution at the power-on reset vector configured during power-on configuration. the processor continues to handle snoop requests during init# assertion. init# is an asynchronous signal and must connect the appropriate pins of all processor fsb agents. 2 lint[1:0] i lint[1:0] (local apic interrupt) must connect the appropriate pins of all fsb agents. when the apic functionality is disabled, the lint0/intr signal becomes intr, a maskable interrupt request signal, and lint1/nmi becomes nmi, a nonmaskable interrupt. intr and nmi are backward compatible with the signals of those names on the pentium ? processor. both signals are asynchronous. these signals must be software configured via bios programming of the apic register space to be used either as nmi/intr or lint[1:0]. because the apic is enabled by default after reset, operation of these pins as lint[1:0] is the default configuration. 2 ll_id[1:0] o the ll_id[1:0] signals are used to select the correct loadline slope for the processor. these signals are not connected to the processor die. lock# i/o lock# indicates to the system that a transaction must occur atomically. this signal must connect the appropriate pins of all processor fsb agents. for a locked sequence of transactions, lock# is asserted from the beginning of the first transaction to the end of the last transaction. when the priority agent asserts bp ri# to arbitrate for ownership of the processor fsb, it will wait un til it observes lock# deasserted. this enables symmetric agents to retain ownership of the processor fsb throughout the bus locked operation and ensure the atomicity of lock. 3 table 5-1. signal definitions (sheet 5 of 8) name type description notes
signal definitions 76 mcerr# i/o mcerr# (machine check erro r) is asserted to indicate an unrecoverable error without a bus protocol violation. it may be driven by all processor fsb agents. mcerr# assertion conditions are configurable at a system level. assertion options are defined by the following options: ? enabled or disabled. ? asserted, if configured, for internal errors along with ierr#. ? asserted, if configured, by th e request initiator of a bus transaction after it observes an error. ? asserted by any bus agent when it observes an error in a bus transaction. for more details regarding machine check architecture, refer to the intel ? 64 and ia-32 architectures software developer?s manual , volume 3. ms_id[1:0] o these signals are provided to indicate the market segment for the processor and may be used for futu re processor compatibility or for keying. these signals are not connected to the processor die. both the bits 0 and 1 are logic 1 and are no connects on the package. prochot# o prochot# (processor hot) will go active when the processor?s temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. this indicates that the thermal control circuit (tcc) has been activated, if enabled. the tcc will remain active until shortly after the processor deasserts prochot#. see section 6.2.3 for more details. pwrgood i pwrgood (power good) is an input. the processor requires this signal to be a clean indication that all processor clocks and power supplies are stable and within thei r specifications. ?clean? implies that the signal will remain low (c apable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. the signal must then transition monotonically to a high state. pwrgood can be driven inactive at any time, but clocks and power mu st again be stable before a subsequent rising edge of pwrgood. it must also meet the minimum pulse width specification in ta b l e 2 - 1 8 , and be followed by a 1-10 ms reset# pulse. the pwrgood signal must be supplied to the processor; it is used to protect internal circuits against vo ltage sequencing issues. it should be driven high throughout boundary scan operation. 2 req[4:0]# i/o req[4:0]# (request command) must connect the appropriate pins of all processor fsb agents. they are asserted by the current bus owner to define the currently active transaction type. these signals are source synchronous to adstb[1:0]#. refer to the ap[1:0]# signal description for details on parity checking of these signals. 3 reset# i asserting the reset# signal resets all processors to known states and invalidates their internal caches without writing back any of their contents. for a power-on reset, reset# must stay active for at least 1 ms after v cc and bclk have reached their proper specifications. on observing active reset#, all fsb ag ents will deassert their outputs within two clocks. reset# must not be kept asserted for more than 10 ms while pwrgood is asserted. a number of bus signals are sampled at the active-to-inactive transition of reset# for power-on configuration. these configuration options are described in the section 7.1 . this signal does not have on-die termination and must be terminated on the system board. 3 rs[2:0]# i rs[2:0]# (response status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of all processor fsb agents. 3 table 5-1. signal definitions (sheet 6 of 8) name type description notes
77 signal definitions rsp# i rsp# (response parity) is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of rs[2:0]#, the signals for which rsp# provides parity protection. it must connect to the appropriate pins of all processor fsb agents. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. while rs[2:0]# = 000, rsp# is also high, si nce this indicates it is not being driven by any agent guaranteeing correct parity. 3 sktocc# o sktocc# (socket occupied) will be pulled to ground by the processor to indicate that the processor is present. there is no connection to the processor silicon for this signal. smi# i smi# (system management interrupt) is asserted asynchronously by system logic. on accepting a system management interrupt, processors save the current state and enter system management mode (smm). an smi ac knowledge transaction is issued, and the processor begins program execution from the smm handler. if smi# is asserted during the de assertion of reset# the processor will tri-state its outputs. see section 7.1 . 2 stpclk# i stpclk# (stop clock), when asserted, causes processors to enter a low power stop-grant state. the processor issues a stop-grant acknowledge transaction, and stops providing internal clock signals to all processor core units except the fsb and apic units. the processor continues to snoop bus transactions and service interrupts while in stop-grant state. wh en stpclk# is deasserted, the processor restarts its internal clock to all units and resumes execution. the assertion of stpclk# has no effect on the bus clock; stpclk# is an asynchronous input. 2 tck i tck (test clock) provides the clock input for the processor test bus (also known as the test access port). tdi i tdi (test data in) transfers serial test data into the processor. tdi provides the serial input needed for jtag specification support. tdo o tdo (test data out) transfers serial test data out of the processor. tdo provides the serial output needed for jtag specification support. testhi[12:10] i testhi[12:10] must be connected to a v tt power source through a resistor for proper processor operation. refer to section 2.6 for testhi grouping restrictions. testin1 testin2 i i testin1 must be connected to a vtt power source through a resistor as well as to the testin2 land of the same socket for proper processor operation. testin2 must be connected to a vtt power source through a resistor as well as to the testin1 land of the same socket for proper processor operation. thermtrip# o assertion of thermtrip# (thermal trip) indicates the processor junction temperature has reached a temperature beyond which permanent silicon damage may occur. measurement of the temperature is accomplished through an internal thermal sensor. upon assertion of thermtrip#, the processor w ill shut off its internal clocks (thus halting program execution) in an attempt to reduce the processor junction temperature. to protect the processor its core voltage (v cc ) must be removed following the assertion of thermtrip#. intel also recommends the removal of v tt when thermtrip# is asserted. driving of the thermtrip# si gnals is enabled within 10 s of the assertion of pwrgood and is disabled on de-assertion of pwrgood. once activated, thermtrip# rema ins latched until pwrgood is de- asserted. while the de-assertion of the pwrgood signal will de- assert thermtrip#, if the processor?s junction temperature remains at or above the trip level, thermt rip# will again be asserted within 10 s of the assertion of pwrgood. 1 table 5-1. signal definitions (sheet 7 of 8) name type description notes
signal definitions 78 notes: 1. for this processor land on the quad-core intel? xeon? processor 5400 series, the maximum number of symmetric agents is one. maximum number of priority agents is zero. 2. for this processor land on the quad-core intel? xeon? processor 5400 series, the maximum number of symmetric agents is two. maximum nu mber of priority agents is zero. 3. for this processor land on the quad-core intel? xeon? processor 5400 series, the maximum number of symmetric agents is two. maximum nu mber of priority agents is one. tms i tms (test mode select) is a jtag specification support signal used by debug tools. see the debug port design guide for intel ? 5000 series chipset memory controller hub (mch) systems (external version) for further information. trdy# i trdy# (target ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. trdy# must connect the appropriate pins of all fsb agents. trst# i trst# (test reset) resets the test access port (tap) logic. trst# must be driven low during power on reset. v ccpll i the quad-core intel? xeon? processor 5400 series implements an on-die pll filter solution. the v ccpll input is used as a pll supply voltage. vcc_die_sense vcc_die_sense2 o vcc_die_sense and vcc_die_sens e2 provides an isolated, low impedance connection to the processor core power and ground. this signal should be connected to the voltage regulator feedback signal, which insures the output voltage (t hat is, processor voltage) remains within specification. please see th e applicable platform design guide for implementation details. vid[6:1] o vid[6:1] (voltage id) pins are used to support automatic selection of power supply voltages (v cc ). these are cmos signals that are driven by the processor and must be pulled up through a resistor. conversely, the voltage regulator outp ut must be disabled prior to the voltage supply for these pins be comes invalid. the vid pins are needed to support processor voltage specification variations. see ta b l e 2 - 4 for definitions of these pins. the vr must supply the voltage that is requested by these pins, or disable itself. vid_select o vid_select is an output from the processor which selects the appropriate vid table for the voltage regulator. this signal is not connected to the processor die. this signal is a no-connect on the quad-core intel? xeon? processor 5400 series package. vss_die_sense vss_die_sense2 o vss_die_sense and vss_die_sense2 provides an isolated, low impedance connection to the processor core power and ground. this signal should be connected to the voltage regulator feedback signal, which insures the output voltage (t hat is, processor voltage) remains within specification. please see th e applicable platform design guide for implementation details. vtt p the fsb termination volt age input pins. refer to ta b l e 2 - 1 2 for further details. vtt_out o the vtt_out signals are includ ed in order to provide a local v tt for some signals that require termination to v tt on the motherboard. vtt_sel o the vtt_sel signal is used to select the correct v tt voltage level for the processor. vtt_sel is connected to vss on the quad-core intel? xeon? processor 5400 series package. table 5-1. signal definitions (sheet 8 of 8) name type description notes
79 thermal specifications 6 thermal specifications 6.1 package thermal specifications the quad-core intel? xeon? processor 5400 series requires a thermal solution to maintain temperatures within its operating limits. any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the sy stem. as processor technology changes, thermal management becomes increasingly crucial when building computer systems. maintaining the proper thermal environment is key to reliable, long-term system operation. a complete solution includes both component and system level thermal management features. component level thermal solutions can include active or passive heatsinks attached to the processor integrated heat sp reader (ihs). typical system level thermal solutions may consist of system fans combined with ducting and venting. this section provides data necessary for de veloping a complete thermal solution. for more information on designing a component level thermal solution, refer to the quad- core intel? xeon? processor 5400 series thermal/mechanical design guidelines (tmdg). note: the boxed processor will ship with a component thermal solution. refer to chapter 8 for details on the boxed processor. 6.1.1 thermal specifications to allow the optimal operation and long-term reliability of intel processor-based systems, the processor must remain within the minimum and maximum case temperature (tcase) specifications as define d by the applicable thermal profile (see ta b l e 6 - 1 and figure 6-1 for the quad-core intel? xeon? processor x5482, ta b l e 6 - 3 and figure 6-2 for the quad-core intel? xeon? processor x5400 series, ta b l e 6 - 6 and figure 6-3 for the quad-core intel? xe on? processor e5400 series, ta b l e 6 - 8 and figure 6-4 for the quad-core intel? xeon? processor l5400 series and ta b l e 6 - 1 1 and figure 6-5 for the quad-core intel? xeon? processor l5408. thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. for more details on thermal solution design, please refer to the quad-core intel? xeon? processor 5400 series thermal/mechanical design guidelines (tmd g) or quad-core intel? xeon? processor l5408 series in embedded applications th ermal/mechanical design guidelines (tmdg) . the quad-core intel? xeon? processor 5400 series implements a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control and to assure processor reliability. selection of the appropriate fan speed is based on the relative temperature data reported by the processor?s platform environment control interface (peci) bus as described in section 6.3 . if the value reported via peci is less than t control , then the case temperature is permitted to exceed the ther mal profile. if the value reported via peci is greater than or equal to t control , then the processor case temperature must remain at or below the temperature as specifie d by the thermal profile. the temperature reported over peci is always a negative value and represents a delta below the onset of thermal control circuit (tcc) activation, as indicated by prochot# (see section 6.2 ,
thermal specifications 80 processor thermal features). systems that implement fan speed control must be designed to use this data. systems that do not alter the fan speed only need to guarantee the case temperature meets the thermal profile specifications. the quad-core intel? xeon? processor x5482, and quad-core intel? xeon? processor e5400 series, and quad-core intel? xeon? processor l5400 series support a single thermal profile (see figure 6-1 , and figure 6-3 and figure 6-4 ; ta b l e 6 - 1 , and ta b l e 6 - 6 , and ta b l e 6 - 8 ). with this thermal profile, it is expected that the thermal control circuit (tcc) would only be activated for very brief periods of time when running the most power-intensive applications. refer to the quad-core intel? xeon? processor 5400 series thermal/mechanical design guidelines (tmdg) for details on system thermal solution design, thermal profiles and environmental considerations. the quad-core intel? xeon? processor l5408 supports a thermal profile with nominal and short-term conditions designed to meet nebs level 3 compliance (see figure 6-5 ). operation at either thermal profile should resu lt in virtually no tcc activation. refer to the quad-core intel? xeon? processor l5408 series in embedded applications thermal/mechanical design guidelines (tmdg) . the quad-core intel? xeon? processor x5400 series supports a dual thermal profile, either of which can be implemented. both ensure adherence to the intel reliability requirements. thermal profile a (see figure 6-2 ; ta b l e 6 - 3 ) is representative of a volumetrically unconstrained thermal solution (that is, industry enabled 2u heatsink). in this scenario, it is expected that the thermal control circuit (tcc) would only be activated for very brief periods of time when running the most power intensive applications. thermal profile b (see figure 6-2 ; ta b l e 6 - 5 ) is indicative of a constrained thermal environment (that is, 1u form factor). because of the reduced cooling capability represented by this thermal soluti on, the probability of tcc activation and performance loss is increased. additionally, utilization of a thermal solution that does not meet thermal profile b will violate the thermal specifications and may result in permanent damage to the processor. intel has developed these thermal profiles to allow customers to choose the thermal solution and environmental parameters that best suit their platform implementation. refer to the quad-core intel? xeon? processor 5400 series thermal/mechanical design guidelines (tmdg) for details on system thermal solution design, thermal profiles and environmental considerations. the upper point of the thermal profile cons ists of the thermal design power (tdp) defined in ta b l e 6 - 1 for the quad-core intel? xeon? processor x5482, ta b l e 6 - 3 for the quad-core intel? xeon? processor x5400 series, ta b l e 6 - 6 for the quad-core intel? xeon? processor e5400 series, and ta b l e 6 - 8 for the quad-core intel? xeon? processor l5400 series and the associated t case values. the lower point of the thermal profile is the t case_max at 0 w power (or no power draw) analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. intel recommends that complete thermal solution designs target the thermal design power (tdp) indicated in ta b l e 6 - 2 for the quad-core intel? xeon? proc essor x5482 (c-step) and quad-core intel? xeon? processor x5492, ta b l e 6 - 4 and ta b l e 6 - 5 for the quad-core intel? xeon? processor x5400 series, ta b l e 6 - 7 for the quad-core intel? xeon? processor e5400 series and ta b l e 6 - 9 quad-core intel? xeon? processor l5400 series instead of the maximum processor power consumption. the thermal monitor feature is intended to help protect the processor in the ev ent that an application exceeds the tdp recommendation for a sustained time period. fo r more details on this feature, refer to section 6.2 . to ensure maximum flexibility for fu ture requirements, systems should be designed to the flexible motherboard (fmb) guidelines, even if a processor with lower
81 thermal specifications power dissipation is currently planned. intel? thermal moni tor 1 and intel? thermal monitor 2 feature must be enable d for the processor to remain within its specifications. notes: 1. these values are specified at v cc_max for all processor frequencies. systems must be designed to ensure the processor is not to be subjected to any static v cc and i cc combination wherein v cc exceeds v cc_max at specified i cc . please refer to the lo adline specifications in section 2.13.1 . 2. thermal design power (tdp) should be used for the processor thermal solution design targets. tdp is not the maximum power that the processor can dissipate. tdp is measured at maximum t case . 3. these specifications are based on silicon characterization. 4. power specifications are defined at all vids found in ta b l e 2 - 3 . the quad-core intel? xeon? processor x5482 may be shipped under multiple vids for each frequency. 5. fmb, or flexible motherboard, guidelines provide a de sign target for meeting all planned processor frequency requirements. 6. the quad-core intel? xeon? processor x5482 is in tended for dual processor workstations only. notes: 1. please refer to ta b l e 6 - 2 for discrete points that constitute the thermal profile. 2. implementation of the quad-core intel? xeon? proces sor x5482 thermal profile should result in virtually no tcc activation. furthermore, ut ilization of thermal solutions that do not meet the processor thermal profile will result in increased probability of tcc ac tivation and may incur measurable performance loss. 3. refer to the quad-core intel? xeon? processor 5400 series thermal/mechanical design guidelines (tmdg) for system and environmental implementation details. table 6-1. quad-core intel? xeon? proces sor x5492 and x5482 (c-step) thermal specifications core frequency thermal design power (w) minimum t case (c) maximum t case (c) notes launch to fmb 150 (x5492 and x5482 c-step) 5see figure 6-1 ; ta b l e 6 - 2 1,2,3,4,5,6 figure 6-1. quad-core intel? xeon? processor x5492 and x5482 (c-step)thermal profile thermal profile (2u) 35 40 45 50 55 60 65 70 75 0 102030405060708090100110120130140150 pow e r [w] tcase [c] thermal profile y = 0.187*x + 35 thermal profile (2u) 35 40 45 50 55 60 65 70 75 0 102030405060708090100110120130140150 pow e r [w] tcase [c] thermal profile y = 0.187*x + 35
thermal specifications 82 table 6-2. quad-core intel? xeon? processor x5492 and x5482 (c-step)thermal profile table power (w) t case_max ( c) 0 35.0 5 35.9 10 36.9 15 37.8 20 38.7 25 39.7 30 40.6 35 41.5 40 42.5 45 43.0 50 44.4 55 45.3 60 46.2 65 47.2 70 48.1 75 49.0 80 50.0 85 50.9 90 51.8 95 52.8 100 53.7 105 54.6 110 55.6 115 56.5 120 57.4 125 58.4 130 59.3 135 60.2 140 61.2 145 62.1 150 63.0
83 thermal specifications notes: 1. these values are specified at v cc_max for all processor frequencies. systems must be designed to ensure the processor is not to be subjected to any static v cc and i cc combination wherein v cc exceeds v cc_max at specified icc. please refer to the loadline specifications in section 2.13.1 . 2. thermal design power (tdp) should be used for the processor thermal solution design targets. tdp is not the maximum power that the processor can dissipate. tdp is measured at maximum t case . 3. these specifications are based on silicon characterization. 4. power specifications are defined at all vids found in ta b l e 2 - 3 . the quad-core intel? xeon? processor x5400 series may be shipped under multiple vids for each frequency. 5. fmb, or flexible motherboard, guidelines provide a de sign target for meeting all planned processor frequency requirements. notes: 1. thermal profile a is representative of a volume trically unconstrained platform. please refer to ta b l e 6 - 4 for discrete points that constitute the thermal profile. 2. implementation of the quad-core intel? xeon? processor x5400 series thermal profile a should result in virtually no tcc activation. furthermor e, utilization of thermal solutions th at do not meet thermal profile a will result in increased probability of tcc activati on and may incur measurab le performance loss. (see section 6.2 for details on tcc activation). 3. thermal profile b is representative of a volumetrically constrained platform. please refer to ta b l e 6 - 5 for discrete points that constitute the thermal profile. 4. implementation of the quad-core intel? xeon? processor x5400 series thermal profile b will result in increased probability of tcc activation and measurab le performance loss. furthermore, utilization of thermal solutions that do not meet thermal profile b do not meet the processor? s thermal specifications and may result in permanent damage to the processor. 5. refer to the quad-core intel? xeon? processor 5400 series thermal/mechanical design guidelines (tmdg) for system and environmental implementation details. table 6-3. quad-core intel? xeon? proces sor x5400 series thermal specifications core frequency thermal design power (w) minimum t case (c) maximum t case (c) notes launch to fmb 120 5 see figure 6-2 ; ta b l e 6 - 4 ; ta b l e 6 - 5 1, 2, 3, 4, 5 figure 6-2. quad-core intel? xeon? proces sor x5400 series ther mal profiles a and b 40 45 50 55 60 65 70 75 0 102030405060708090100110120 pow e r [w] tcase [c] tcase_max is a thermal solution design point. in actuality, units will not significantly e xceed tcase_max_a due to tcc activation. thermal profile a y = 0.168*x + 42.8 thermal profile b y = 0.221*x + 43.5 40 45 50 55 60 65 70 75 0 102030405060708090100110120 pow e r [w] tcase [c] 40 45 50 55 60 65 70 75 0 102030405060708090100110120 pow e r [w] tcase [c] tcase_max is a thermal solution design point. in actuality, units will not significantly e xceed tcase_max_a due to tcc activation. thermal profile a y = 0.168*x + 42.8 thermal profile b y = 0.221*x + 43.5
thermal specifications 84 table 6-4. quad-core intel? xeon? processor x5400 series ther mal profile a table power (w) t case_max ( c) 0 42.8 5 43.6 10 44.5 15 45.3 20 46.2 25 47.0 30 47.8 35 48.7 40 49.5 45 50.0 50 51.2 55 52.0 60 52.9 65 53.7 70 54.6 75 55.4 80 56.2 85 57.1 90 57.9 95 58.8 100 59.6 105 60.4 110 61.3 115 62.1 120 63.0
85 thermal specifications notes: 1. these values are specified at v cc_max for all processor frequencies. systems must be designed to ensure the processor is not to be subjected to any static vcc and icc combination wherein vcc exceeds v cc_max at specified icc. please refer to the loadline specifications in section 2.13 . 2. thermal design power (tdp) should be used for the processor thermal solution design targets. tdp is not the maximum power that the processor can dissipate. tdp is measured at maximum t case . 3. these specifications are based on silicon characterization. 4. power specifications are defined at all vids found in ta b l e 2 - 1 2 . the quad-core intel? xeon? processor e5400 series may be shipped under multiple vids for each frequency. 5. fmb, or flexible motherboard, guidelines provide a de sign target for meeting all planned processor frequency requirements. table 6-5. quad-core intel? xeon? processor x5400 series thermal profile b table power (w) t case_max ( c) 0 43.5 5 44.6 10 45.7 15 46.8 20 47.9 25 49.0 30 50.1 35 51.2 40 52.3 45 53.4 50 54.6 55 55.7 60 56.8 65 57.9 70 59.0 75 60.1 80 61.2 85 62.3 90 63.4 95 64.5 100 65.6 105 66.7 110 67.8 115 68.9 120 70.0 table 6-6. quad-core intel? xeon? proces sor e5400 series thermal specifications core frequency thermal design power (w) minimum t case (c) maximum t case (c) notes launch to fmb 80 5 see figure 6-3 ; ta b l e 6 - 7 1, 2, 3, 4, 5
thermal specifications 86 notes: 1. please refer to ta b l e 6 - 7 for discrete points that c onstitute the thermal profile. 2. implementation of the quad-core intel? xeon? pr ocessor 5400 series thermal profile should result in virtually no tcc activation. furthermore, utilization of thermal solutions that do not meet the processor thermal profile will result in increased probability of tcc activation and may incur measurable performance loss. (see section 6.2 for details on tcc activation). 3. refer to the quad-core intel? xeon? processor 5400 series thermal/mechanical design guidelines (tmdg) for system and environmental implementation details. figure 6-3. quad-core intel? xeon? pr ocessor e5400 series thermal profile 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 0 1020304050607080 pow e r [w] tcase [c] thermal profile y = 0.298*x + 43.2 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 0 1020304050607080 pow e r [w] tcase [c] thermal profile y = 0.298*x + 43.2 table 6-7. quad-core intel? xeon? proce ssor e5400 series thermal profile table (sheet 1 of 2) power (w) t case_max ( c) 0 43.5 5 45.0 10 46.4 15 47.9 20 49.4 25 50.9 30 52.3 35 53.8 40 55.3 45 56.7 50 58.2 55 59.7 60 61.1 65 62.6
87 thermal specifications notes: 1. these values are specified at v cc_max for all processor frequencies. systems must be designed to ensure the processor is not to be subjected to any static vcc and icc combination wherein vcc exceeds v cc_max at specified icc. please refer to the loadline specifications in section 2.13 . 2. thermal design power (tdp) should be used for processor thermal solution design targets. tdp is not the maximum power that the processor can di ssipate. tdp is measured at maximum t case . 3. these specifications are based pre-silicon estimates and simulations. these spec ifications will be updated with characterized data from silicon measurem ents in a future release of this document. 4. power specifications are defined at all vids found in ta b l e 2 - 1 2 . the quad-core intel? xeon? processor l5400 series may be shipped under multiple vids for each frequency. 5. fmb, or flexible motherboard, guidelines provide a de sign target for meeting all planned processor frequency requirements. notes: 1. please refer to ta b l e 6 - 9 for discrete points that constitute the thermal profile. 2. implementation of the quad-core intel? xeon? proc essor l5400 series thermal profile should result in virtually no tcc activation. furthermore, utilization of thermal solutions that do not meet the processor thermal profile will result in increa sed probability of tcc activation and may incur measurable performance loss. (see section 6.2 for details on tcc activation). 3. refer to the quad-core intel? xeon? processor 5400 series thermal/mechanical design guidelines (tmdg) for system and environmental implementation details. 70 64.1 75 65.6 80 67.0 table 6-8. quad-core intel? xeon? proces sor l5400 series thermal specifications core frequency thermal design power (w) minimum t case (c) maximum t case (c) notes launch to fmb 50 5 see figure 6-4 ; ta b l e 6 - 9 1, 2, 3, 4, 5 table 6-7. quad-core intel? xeon? proces sor e5400 series thermal profile table (sheet 2 of 2) power (w) t case_max ( c) figure 6-4. quad-core intel? xeon? pr ocessor l5400 series thermal profile 40 42 44 46 48 50 52 54 56 58 60 0 1020304050 pow e r [w] tcase [c] thermal profile y = 0.298*x + 42.1 40 42 44 46 48 50 52 54 56 58 60 0 1020304050 pow e r [w] tcase [c] thermal profile y = 0.298*x + 42.1
thermal specifications 88 notes: 1. these values are specified at v cc_max for all processor frequencies. syst ems must be designed to ensure the processor is not to be subjected to any static vcc and icc combination wherein vcc exceeds v cc_max at specified icc. please refer to the loadline spec ifications in section 2.13 . 2. thermal design power (tdp) should be used for proc essor thermal solution design targets. tdp is not the maximum power that the processor can diss ipate. tdp is measured at maximum t case . 3. these specifications are based pre-silicon estimates and simulation s. these specificatio ns will be updated with characterized data from silicon measurem ents in a future release of this document. 4. power specifications are defined at all vids found in ta b l e 2 - 1 2 . the quad-core intel? xeon? processor l5408 may be shipped under multiple vids for each frequency. 5. fmb, or flexible motherboard, guidelines provide a design target for meeting all planned processor frequency requirements. table 6-9. quad-core intel? xeon? proce ssor l5400 series th ermal profile table power (w) t case_max ( c) 0 42.1 5 43.6 10 45.1 15 46.6 20 48.1 25 49.6 30 51.0 35 52.5 40 54.0 45 55.5 50 57.0 table 6-10. quad-core intel? xeon? pr ocessor l5408 thermal specifications core frequency thermal design power (w) minimum t case (c) maximum t case (c) notes launch to fmb 40 5 see figure 6-5 ; ta b l e 6 - 1 1 1, 2, 3, 4, 5
89 thermal specifications notes: 1. please refer to ta b l e 6 - 1 1 for discrete points that constitute the thermal profile. 2. implementation of the quad-core intel? xeon? processor l5408 thermal profile should result in virtually no tcc activation. furthermore, ut ilization of thermal solutions that do not meet the processor thermal profile will result in increased probability of tcc ac tivation and may incur measurable performance loss. (see section 6.2 for details on tcc activation). 3. the nominal thermal profile must be used for all normal operating conditions, or for products that do not require nebs level 3 compliance. 4. the short-term thermal profile may only be used for short-term excursions to higher ambient operating temperatures, not to exceed 96 hours per instance , 360 hours per year, and a maximum of 15 instances per year, as compliant with nebs level 3. 5. utilization of a thermal solution that exceeds the short-term thermal profile, or which operates at the short-term thermal profile for a duration longer than the limits specified in note 4 above, do not meet the processor?s thermal specificatio ns and may result in permanent damage to the processor. 6. refer to the quad-core intel? xeon? processor l5408 series in embedded applications thermal/mechanical desi gn guidelines (tmdg) for system and environmental implementation details. figure 6-5. quad-core intel? xeon ? processor l5408 thermal profile thermal profile 40 50 60 70 80 90 0 5 10 15 20 25 30 35 40 power [w] tcase [c] short-term thermal prof ile tc = 0.678 * p + 60 no min a l th e r ma l pr o f il e tc = 0.678 * p + 45 short-term thermal prof ile may only be used f or short term excursions to higher ambient temperatures, not to exceed 360 hours per year table 6-11. quad-core intel? xeon? pr ocessor l5408 thermal profile table power (w) nominal t case_max ( c) short-term t case_max ( c) 04560 54863 10 52 67 15 55 70 20 59 74 25 62 77 30 65 80 35 69 84 40 72 87
thermal specifications 90 6.1.2 thermal metrology the minimum and maximum case temperatures (t case ) are specified in ta b l e 6 - 2 , ta b l e 6 - 4 , ta b l e 6 - 5 , and ta b l e 6 - 7 , and ta b l e 6 - 9 and ta b l e 6 - 1 1 are measured at the geometric top center of the processo r integrated heat spreader (ihs). figure 6-6 illustrates the location where t case temperature measurements should be made. for detailed guidelines on temperature me asurement methodology, refer to the quad-core intel? xeon? processor 5400 series thermal/mechanical design guidelines (tmdg). note: figure is not to scale and is for reference only. 6.2 processor thermal features 6.2.1 intel ? thermal monitor features quad-core intel? xeon? processor 5400 series provides two thermal monitor features, intel? thermal monitor 1 and intel? thermal monitor 2. the intel? thermal monitor 1 and intel? thermal monitor 2 must both be enabled in bios for the processor to be operating within specificatio ns. when both are enabled, intel? thermal monitor 2 will be activated first and intel? thermal monitor 1 will be added if intel? thermal monitor 2 is not effective. 6.2.1.1 intel? thermal monitor 1 the intel? thermal monitor 1 feature help s control the processor temperature by activating the thermal control circuit (tcc) when the processor silicon reaches its maximum operating temperature. the tcc reduces processor power consumption as figure 6-6. case temperature (t case ) measurement location
91 thermal specifications needed by modulating (starting and stopping) the internal processor core clocks. the temperature at which the intel? thermal monitor 1 activates the thermal control circuit is not user configurable and is not software visible. bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the tcc is active. when the intel? thermal monitor 1 is enable d, and a high temperature situation exists (that is, tcc is active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor (typically 30 - 50%). cycle times are processor speed dependent and will decrease as processor core frequencies increase. a small amount of hysteresis has been included to prevent rapid active/inactive transitions of the tcc when the processor temperature is near its maximum operating temperature. once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the tcc goes inactive and clock modulation ceases. with thermal solutions designed to the quad-core intel? xeon ? processor x5482, quad-core intel? xeon? processor x5400 series, and quad-core intel? xeon? processor e5400 series, and quad-core inte l? xeon? processor l5400 series thermal profile, it is anticipated that the tcc would only be activated for very short periods of time when running the most power intensiv e applications. the pr ocessor performance impact due to these brief periods of tcc activation is expected to be so minor that it would be immeasurable. refer to the quad-core intel? xeon? processor 5400 series thermal/mechanical design guidelines (tmdg) for information on designing a thermal solution. the duty cycle for the tcc, when activated by the intel? thermal monitor 1, is factory configured and cannot be modified. the intel? thermal monitor 1 does not require any additional hardware, software drivers, or interrupt handling routines. 6.2.1.2 intel? thermal monitor 2 the quad-core intel? xeon? processor 5400 series adds supports for an enhanced thermal monitor capability known as intel? thermal monitor 2). this mechanism provides an efficient means for limiting th e processor temperature by reducing the power consumption within the processor. inte l? thermal monitor 2 requires support for dynamic vid transitions in the platform. note: not all quad-core intel? xeon? processor 5400 series are capable of supporting intel? thermal monitor 2. more detail on which processor frequencies will support intel? thermal monitor 2 will be pr ovided in future releases of the quad-core intel? xeon? processor 5400 series thermal/mechanical design guidelines (tmdg) when available. for more details also refer to the intel? 64 and ia-32 architectures software developer?s manual . when intel? thermal monitor 2 is enabled, and a high temperature situation is detected, the thermal control circuit (tcc) will be activated for both processor cores. the tcc causes the processor to adjust its operating frequency (via the bus multiplier) and input voltage (via the vid signals). this combination of reduced frequency and vid results in a reduction to the processor power consumption. a processor enabled for intel? thermal monitor 2 includes two operating points, each consisting of a specific operating frequenc y and voltage, which is identical for both processor cores. the first operating point represents the normal operating condition for the processor. under this condition, the core-frequency-to-system-bus multiplier utilized by the processor is that containe d in the clock_flex_max msr and the vid that is specified in ta b l e 2 - 3 .
thermal specifications 92 the second operating point consists of both a lower operating frequency and voltage. the lowest operating frequency is determined by the lowest supported bus ratio (1/6 for the quad-core intel? xeon? processor 540 0 series). when the tcc is activated, the processor automatically transitions to th e new frequency. this transition occurs rapidly, on the order of 5 s. during the frequency transition, the processor is unable to service any bus requests, and consequently, all bus traffic is blocked. edge-triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency. once the new operating frequency is engaged, the processor will transition to the new core operating voltage by issuing a new vid code to the voltage regulator. the voltage regulator must support dynamic vid steps in order to support intel? thermal monitor 2. during the voltage change, it will be ne cessary to transition through multiple vid codes to reach the target operating voltage. each step will be one vid table entry (see ta b l e 2 - 3 ). the processor continues to execute instructions during the voltage transition. operation at the lower voltage reduces the power consumption of the processor. a small amount of hysteresis has been in cluded to prevent rapid active/inactive transitions of the tcc when the processor temperature is near its maximum operating temperature. once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the operating frequency and voltage transition back to the normal system operating point. transition of the vid code will occur first, in order to insure proper operation once the processor reaches its normal operating frequency. refer to figure 6-7 for an illustration of this ordering. the prochot# signal is asserted when a high temperature situation is detected, regardless of whether intel? thermal monitor 1 or intel? thermal monitor 2 is enabled. 6.2.2 on-demand mode the processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumptio n. this mechanism is referred to as ?on- demand? mode and is distinct from the intel? thermal monitor 1 and intel? thermal monitor 2 features. on-demand mode is intended as a means to reduce system level power consumption. systems utilizing the quad-core intel? xeon? processor 5400 figure 6-7. intel? thermal monito r 2 frequency and voltage ordering vcc temperature v nom frequency time f tm2 f max t tm2 v tm2 t(hysterisis) vcc temperature v nom frequency time f tm2 f max t tm2 v tm2 t(hysterisis)
93 thermal specifications series must not rely on software usage of this mechanism to limit the processor temperature. if bit 4 of the ia32_clock _modulation msr is set to a ?1?, the processor will immediately reduce its power consumption via modulation (starting and stopping) of the internal core clock, inde pendent of the processor temperature. when using on-demand mode, the duty cycle of th e clock modulation is programmable via bits 3:1 of the same ia32_clock_modulat ion msr. in on-demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off to 87.5% on/12.5% off in 12.5% increments. on-demand mode may be used in conjunction with the thermal monitor; however, if the system tries to enable on-demand mode at the same time the tcc is engaged, the factory configured duty cycle of the tcc will override the duty cycle selected by the on-demand mode. 6.2.3 prochot# signal an external signal, prochot# (processor hot) is asserted when the processor die temperature of any processor cores reaches its factory configured trip point. if thermal monitor is enabled (note that thermal monitor must be enabled for the processor to be operating within specification), the tcc will be active when prochot# is asserted. the processor can be configured to generate an interrupt upon the assertion or de- assertion of prochot#. refer to the intel? 64 and ia-32 architectures software developer?s manual for specific register and programming details. prochot# is designed to assert at or a few degrees higher than maximum t case when dissipating tdp power, and cannot be interpreted as an indication of processor case temperature. this temperature delta acco unts for processor package, lifetime and manufacturing variations and attempts to ensure the thermal control circuit is not activated below maximum t case when dissipating tdp power. there is no defined or fixed correlation between the prochot# trip temperature, or the case temperature. thermal solutions must be designed to the processor specifications and cannot be adjusted based on experimental measurements of t case , or prochot#. 6.2.4 forcepr# signal the forcepr# (force power reduction) input can be used by the platform to cause the quad-core intel? xeon? processor 5400 series to activate the tcc. if the thermal monitor is enabled, the tcc will be activa ted upon the assertion of the forcepr# signal. assertion of the forcepr# signal will activate tcc for all processor cores. the tcc will remain active until the system deasserts forcepr#. forcepr# is an asynchronous input. forcepr# can be us ed to thermally protect other system components. to use the vr as an exampl e, when forcepr# is asserted, the tcc circuit in the processor will activate, reducing the current consumption of the processor and the corresponding temperature of the vr. it should be noted that assertion of forcepr# does not automatically assert prochot#. as mentioned previously, the proc hot# signal is asserted when a high temperature situation is detected. a minimum pulse width of 500 s is recommended when forcepr# is asserted by the system . sustained activation of the forcepr# signal may cause noticeable platform performance degradation. refer to the appropriate platform design guidelines for details on implementing the forcepr# signal feature.
thermal specifications 94 6.2.5 thermtrip# signal regardless of whether or not intel? thermal monitor 1 or intel? thermal monitor 2 is enabled, in the event of a catastrophic c ooling failure, the proce ssor will automatically shut down when the silicon has reached an elevated temperature (refer to the thermtrip# definition in ta b l e 5 - 1 ). at this point, the fsb signal thermtrip# will go active and stay active as described in ta b l e 5 - 1 . thermtrip# activation is independent of processor activity and does not generate any bus cycles. intel also recommends the removal of v tt . 6.3 platform environment control interface (peci) 6.3.1 introduction peci offers an interface for thermal mo nitoring of intel processor and chipset components. it uses a single wire, thus alleviating routing congestion issues. figure 6-8 shows an example of the peci topology in a system with quad-core intel? xeon? processor 5400 series. peci uses crc checking on the host side to ensure reliable transfers between the host and client devices. also, data transfer speeds across the peci interface are negotiable within a wide range (2kbps to 2mbps). the peci interface on the quad-core intel? xeon? proc essor 5400 series is disabled by default and must be enabled through bios. 6.3.1.1 t control and tcc activation on peci-based systems fan speed control solutions based on peci utilize a t control value stored in the processor ia32_temperature_target msr. the t control msr uses the same offset temperature format as peci though it contains no sign bit. thermal management devices should infer the t control value as negative. thermal management algorithms figure 6-8. quad-core intel? xeon? processor 5400 series peci topology peci host controller domain0 0 x 3 0 domain1 0 x 3 0 domain0 0 x 3 1 domain1 0 x 3 1 processor (socket 0) processor (socket 1) g5 g5
95 thermal specifications should utilize the relative temperature value de livered over peci in conjunction with the t control msr value to control or optimize fan speeds. figure 6-9 shows a conceptual fan control diagram using peci temperatures. the relative temperature value reported over peci represents the data below the onset of thermal control circuit (tcc) activation as needed by prochot# assertions. as the temperature approaches tcc activation, the peci value approaches zero. tcc activates at a peci count of zero. 6.3.1.2 processor thermal data sample rate and filtering the digital thermal sensor (dts) provides an improved capability to monitor device hot spots, which inherently leads to more va rying temperature readings over short time intervals. the dts sample interval range can be modified, and a data filtering algorithm can be activated to help moderate this. the dts sample interval range is 82us (default) to 20 ms (max). this value can be set in bios. to reduce the sample rate requirements on peci and improve thermal data stability vs. time the processor dts also implements an averaging algorithm that filters the incoming data. this is an alpha-beta filter with coefficients of 0.5, and is expressed mathematically as: current_filtered_tem p = (previous_filtered_temp / 2) + (new_sensor_temp / 2). this filtering algorith m is fixed and cannot be changed. it is on by default and can be turned off in bios. host controllers should utilize the min/max sample times to determine the appropriate sample rate based on the controller's fan control algorithm and targeted response rate. the key items to take into account when settling on a fan control algorithm are the dts sample rate, whether the temperature filter is enabled, how often the peci host will poll the processor for temperature data, and the rate at which fan speed is changed. depending on the designer?s specific requir ements the dts sample rate and alpha-beta filter may have no effect on the fan control algorithm. figure 6-9. conceptual fan control diagram of peci-based platforms fan speed (rpm) (not intended to depict actual implementation) max min temperature peci = -10 peci = -20 tcc activation temperature t control setting peci = 0 fan speed (rpm) (not intended to depict actual implementation) max min temperature peci = -10 peci = -20 tcc activation temperature t control setting peci = 0
thermal specifications 96 6.3.2 peci specifications 6.3.2.1 peci device address the peci device address for socket 0 is 0x30 and socket 1 is 0x31. please note that each address also supports two domains (domain0 and domain1). for more information on peci domains, please refer to the platform environment control interface (peci) specification . 6.3.2.2 peci command support peci command support is covered in detail in platform environment control interface specification. please refer to this document fo r details on supported peci command function and codes. 6.3.2.3 peci fault handling requirements peci is largely a fault tolerant interface, including noise immunity and error checking improvements over other comparable industry standard interfaces. the peci client is as reliable as the device that it is embe dded in, and thus given operating conditions that fall under the specification, the peci will always respond to requests and the protocol itself can be relied upon to detect any transmission failures. there are, however, certain scenarios where peci is known to be unresponsive. prior to a power on reset# and during rese t# assertion, peci is not guaranteed to provide reliable thermal data. system designs should implement a default power-on condition that ensures proper processor operation during the time frame when reliable data is not available via peci. to protect platforms from potential operational or safety issues due to an abnormal condition on peci, the host controller should take action to protect the system from possible damage. it is recommended that the peci host controller take appropriate action to protect the client processor device if valid temperature readings have not been obtained in response to three consecutive gettemp()s or for a one second time interval. the host controller may also implemen t an alert to software in the event of a critical or continuous fault condition. 6.3.2.4 peci gettemp0() and ge ttemp1() error code support the error codes supported for the processor gettemp0() and gettemp1() commands are listed in ta b l e 6 - 1 2 below: table 6-12. gettemp0() gettemp1()error codes error code description 0x8000h general sensor error 0x8002h sensor is operational, but has detected a temperature below its operational range (underflow).
97 features 7 features 7.1 power-on configuration options several configuration options can be config ured by hardware. the quad-core intel? xeon? processor 5400 series samples its hardware configuration at reset, on the active-to-inactive transition of reset#. for specifics on these options, please refer to ta b l e 7 - 1 . the sampled information configures the processor for subsequent operation. these configuration options cannot be changed except by another reset. all external resets reconfigure the processor, for configuration purposes, the processor does not distinguish between a ?warm? reset (pwrgood signal remains asserted) and a ?power-on? reset. notes: 1. asserting this signal du ring reset# will select the correspond ing option. 2. address lands not identified in this table as configuration options should not be asserted during reset#. disabling of any of the cores within the quad-core intel? xeon? processor 5400 series must be handled by configuring the ext_config model specific register (msr). this msr will allow for the disabling of a single core per die within the package. 7.2 clock control and low power states the quad-core intel? xeon? processor 5400 se ries supports the extended halt state (also referred to as c1e) in addition to th e halt state and stop-grant state to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. see figure 7-1 for a visual representation of the processor low power states. the extended halt state is a lower power state than the halt state or stop grant state. the extended halt state must be enab led via the bios for the processor to remain within its specifications. for processors that are already running at the lowest bus to core frequency ratio for its nominal operating point, the processor will transition to the halt state instead of the extended halt state. the stop grant state requires chipset and bios support on multiprocessor systems. in a multiprocessor system, all the stpclk# signals are bussed together, thus all processors are affected in unison. when the stpclk# signal is asserted, the processor enters the stop grant state, issuing a stop grant special bus cycle (sbc) for each processor die. the chipset needs to account for a variable number of processors asserting the stop grant sbc on the bus before allowing the processor to be transitioned into one of the lower processor power states. table 7-1. power-on configuration option lands configuration option land name notes output tri state smi# 1,2 execute bist (built-in self test) a3# 1,2 disable mcerr# observation a9# 1,2 disable binit# observation a10# 1,2 symmetric agent arbitration id br[1:0]# 1,2
features 98 7.2.1 normal state this is the normal operating state for the processor. 7.2.2 halt or extended halt state the extended halt state (c1e) is enabled via the bios. the extended halt state must be enabled for the processor to remain within its specifications. the extended halt state requires support for dynamic vid transitions in the platform. 7.2.2.1 halt state halt is a low power state entered when the processor have executed the halt or mwait instruction. when one of the processor cores execute the halt or mwait instruction, that processor core is halted; however, the other processor continues normal operation. the processor will transiti on to the normal state upon the occurrence of smi#, binit#, init#, lint[1:0] (nmi, in tr), or an interrupt delivered over the front side bus. reset# will cause the processor to immediately initialize itself. the return from a system management interrupt (smi) handler can be to either normal mode or the halt state. see the intel ? 64 and ia-32 architecture software developer's manual . the system can generate a stpclk# while the processor is in the halt state. when the system deasserts stpclk#, the processor will return execution to the halt state. while in halt state, the processor will pr ocess front side bus snoops and interrupts. 7.2.2.2 extended halt state extended halt state is a low power state entered when all processor cores have executed the halt or mwait instructions and extended halt state has been enabled via the bios. when one of the processor cores executes the halt instruction, that processor core is halted; however, the other processor core continues normal operation. the extended halt state is a lowe r power state than the halt state or stop grant state. the extended halt state must be enabled for the processor to remain within its specifications. the processor will automatically transition to a lower core frequency and voltage operating point before entering the extended halt state. note that the processor fsb frequency is not altered; only the internal core frequency is changed. when entering the low power state, the processor will first switch to the lower bus to core frequency ratio and then transition to the lower voltage (vid). while in the extended halt state, the processor will process bus snoops.
99 features notes: 1. processors running in the lowest bus ratio supported as shown in ta b l e 2 - 1 , will enter the halt state when the processor has executed the halt or mwait instruction since the processor is already operating in the lowest core frequency and voltage operating point. 2. the specification is at tcase = 40 o c and nominal vcc. the vid setting represents the maximum expected vid when running in halt state. 3. skus with extended halt state (16w) and without extended halt state (20w). 4. the specification is at tcase = 46 o c and nominal vcc. the vid setting represents the maximum expected vid when running in halt state. the processor exits the extended halt st ate when a break event occurs. when the processor exits the extended halt state, it will first transition the vid to the original value and then change the bus to core frequency ratio back to the original value. table 7-2. extended halt maximum power symbol parameter min typ max unit notes 1 p extended_halt quad-core intel? xeon? processor x5482 extended halt state power 16 w 2 p extended_halt quad-core intel? xeon? processor x5400 series extended halt state power 16 w 2 p extended_halt quad-core intel? xeon? processor e5400 series extended halt state power 16/20 w 2,3 p extended_halt quad-core intel? xeon? processor l5400 series extended halt state power 12 w 2 p extended_halt quad-core intel? xeon? processor l5408 extended halt state power 12 w 4
features 100 7.2.3 stop-grant state when the stpclk# pin is asserted, the stop-g rant state of the processor is entered no later than 20 bus clocks afte r the response phase of the processor issued stop grant acknowledge special bus cycle. by defaul t, the quad-core intel? xeon? processor 5400 series will issue two stop grant acknowledge special bus cycles, one for each die. once the stpclk# pin has been asserted, it may only be deasserted once the processor is in the stop grant state. all processor cores will enter the stop-grant state once the stpclk# pin is asserted. additionally, all processor cores must be in the stop grant state before the deassertion of stpclk#. since the agtl+ signal pins receive power from the front side bus, these pins should not be driven (allowing the level to return to v tt ) for minimum power drawn by the termination resistors in this state. in additi on, all other input pins on the front side bus should be driven to the inactive state. binit# will not be serviced while the processo r is in stop-grant state. the event will be latched and can be serviced by software upon exit from the stop grant state. reset# will cause the processor to immediately initialize itself, but the processor will stay in stop-grant state. a transition back to the normal state will occur with the de- assertion of the stpclk# signal. a transition to the grant snoop state will o ccur when the processor detects a snoop on the front side bus (see section 7.2.4.1 ). figure 7-1. stop clock state machine extended halt or halt state bclk running snoops and interrupts allowed normal state normal execution extended halt snoop or halt snoop state bclk running service snoops to caches stop grant state bclk running snoops and interrupts allowed snoop event occurs snoop event serviced init#, binit#, intr, nmi, smi#, reset#, fsb interrupts stpclk# asserted stpclk# de-asserted s t p c l k # a s s e r t e d s t p c l k # d e - a s s e r t e d snoop event occurs snoop event serviced halt or mwait instruction and halt bus cycle generated stop grant snoop state bclk running service snoops to caches
101 features while in the stop-grant state, smi#, init#, binit# and lint[1:0] will be latched by the processor, and only serviced when the pr ocessor returns to the normal state. only one occurrence of each event will be recognized upon return to the normal state. while in stop-grant state, the processor will process snoops on the front side bus and it will latch interrupts delivered on the front side bus. the pbe# signal can be driven when the proc essor is in stop-grant state. pbe# will be asserted if there is any pending interrupt latched within the processor. pending interrupts that are blocked by the eflags.if bit being clear will still cause assertion of pbe#. assertion of pbe# indicates to system lo gic that it should return the processor to the normal state. 7.2.4 extended halt snoop or halt snoop state, stop grant snoop state the extended halt snoop state is used in co njunction with the extended halt state. if the extended halt state is not enabled in the bios, the default snoop state entered will be the halt snoop state. refer to the sections below for details on halt snoop state, stop grant snoop state and extended halt snoop state. 7.2.4.1 halt snoop state, stop grant snoop state the processor will respond to snoop or interrupt transactions on the front side bus while in stop-grant state or in halt state. during a snoop or interrupt transaction, the processor enters the halt/grant snoop state. the processor will stay in this state until the snoop on the front side bus has been serv iced (whether by the processor or another agent on the front side bus) or the interru pt has been latched. after the snoop is serviced or the interrupt is latched, the proc essor will return to the stop-grant state or halt state, as appropriate. 7.2.4.2 extended halt snoop state the extended halt snoop state is the default snoop state when the extended halt state is enabled via the bios. the processor will remain in the lower bus to core frequency ratio and vid operating po int of the extended halt state. while in the extended halt snoop state, sn oops and interrupt transactions are handled the same way as in the halt snoop state. afte r the snoop is serviced or the interrupt is latched, the processor will return to the extended halt state. 7.3 enhanced intel speedstep ? technology quad-core intel? xeon? processor 5400 series supports enhanced intel speedstep ? technology. this technology enables the processor to switch between multiple frequency and voltage points, which results in platform power savings. enhanced intel speedstep technology requires support for dynamic vid transitions in the platform. switching between voltage/frequency states is software controlled. for more configuration details also refer to the intel? 64 and ia-32 architectures software developer?s manual . note: not all quad-core intel? xeon? processor 5400 series are capable of supporting enhanced intel speedstep technology. more details on which processor frequencies will support this feature will be provided in the quad-core intel? xeon? processor 5400 series specification update .
features 102 enhanced intel speedstep technology creates processor performance states (p-states) or voltage/frequency operating points which are lower power capability states within the normal state (see figure 7-1 for the stop clock state machine for supported p- states). enhanced intel speedstep techno logy enables real-time dynamic switching between frequency and voltage points. it al ters the performance of the processor by changing the bus to core frequency ratio and voltage. this allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system . the quad-core intel? xeon? processor 5400 series has hardware logic that coordinates the requested voltage (vid) between the processor cores. the highest voltage that is requested for either of the processor cores is selected for that processor package. note that the front side bus is not altered; only the internal core frequency is chan ged. in order to run at reduced power consumption, the voltage is altered in step with the bus ratio. the following are key features of enhanced intel speedstep technology: ? multiple voltage/frequency operating points provide optimal performance at reduced power consumption. ? voltage/frequency selection is software controlled by writing to processor msr?s (model specific registers), thus eliminating chipset dependency. ? if the target frequency is higher than the current frequency, v cc is incremented in steps (+12.5 mv) by placing a new value on the vid signals and the processor shifts to the new frequency. note that the top frequency for the processor can not be exceeded. ? if the target frequency is lower than th e current frequency, the processor shifts to the new frequency and v cc is then decremented in steps (-12.5 mv) by changing the target vid through the vid signals.
103 boxed processor specifications 8 boxed processor specifications 8.1 introduction intel boxed processors are intended for system integrators who build systems from components available through distribution channels. the quad-core intel? xeon? processor 5400 series will be offered as an intel boxed processor. intel will offer the quad-core intel? xeon? processor 5400 series with two heat sink configurations available for each processor frequency: 1u passive/3u+ active combination solution and a 2u passive only solution. the 1u passive/3u+ active combination solution is based on a 1u passive heat sink with a removable fan that will be pre-attached at shipping. this heat sink so lution is intended to be used as either a 1u passive heat sink, or a 3u+ active he at sink. although the active combination solution with removable fan mechanically fits into a 2u keepout, its use is not recommended in that configuration. quad-core intel? xeon? processor x5400 series will include a copper 1u passive/3u+ active combination solution or a copper 2u passive heatsink. quad-core intel? xeon? processor e5400 series and quad-core inte l? xeon? processor l5400 series with 80w and lower tdps will include an alum inum extruded 1u passive/3u+ active combination solution or an aluminum extruded 2u passive heatsink. the 1u passive/3u+ active combination solution in the active fan configuration is primarily designed to be used in a pedestal chassis where sufficient air inlet space is present and strong side directional airflow is not an issue. the 1u passive/3u+ active combination solution with the fan removed an d the 2u passive thermal solution require the use of chassis ducting and are targeted for use in rack mount or pedestal servers. the retention solution used for these products is called the common enabling kit, or cek. the cek base is compatible with both thermal solutions and uses the same hole locations as the intel ? xeon ? processor with 800 mhz system bus. the 1u passive/3u+ active combination solution will utilize a removable fan capable of 4-pin pulse width modulated (pwm) control. use of a 4-pin pwm controlled active thermal solution helps customers meet acoustic targets in pedestal platforms through the motherboards?s ability to directly contro l the rpm of the processor heat sink fan. see section 8.3 for more details on fan speed control, and see section 6.3 for more on the pwm and peci interface along with digital thermal sensors (dts). figure 8-1 through figure 8-3 are representations of the two heat sink solutions.
boxed processor specifications 104 figure 8-1. boxed quad-core inte l? xeon? processor 5400 series 1u passive/3u+ active combination heat sink (with removable fan) figure 8-2. boxed quad-core intel? xeon? pr ocessor 5400 series 2u passive heat sink
105 boxed processor specifications notes: 1. the heat sinks represented in these images are for reference only, and may not represent the final boxed processor heat sinks. 2. the screws, springs, and standoffs will be captive to the heat sink. this image shows all of the components in an exploded view. 3. it is intended that the cek spring will ship with the base board and be pre-attached prior to shipping. 8.2 mechanical specifications this section documents the mechanical specifications of the boxed processor. 8.2.1 boxed processor heat sink dimensions (cek) the boxed processor will be shipped with an unattached thermal solution. clearance is required around the thermal solution to en sure unimpeded airflow for proper cooling. the physical space requirements and dimensions for the boxed processor and assembled heat sink are shown in figure 8-4 through figure 8-8 . figure 8-9 through figure 8-10 are the mechanical drawings for the 4-pin board fan header and 4-pin connector used for the active cek fan heat sink solution. figure 8-3. 2u passive quad-core intel? xeon? processor 5400 series thermal solution (exploded view)
boxed processor specifications 106 figure 8-4. top side board keepout zones (part 1)
107 boxed processor specifications figure 8-5. top side board keepout zones (part 2)
boxed processor specifications 108 figure 8-6. bottom side board keepout zones
109 boxed processor specifications figure 8-7. board mounting-hole keepout zones
boxed processor specifications 110 figure 8-8. volumetric height keep-ins
111 boxed processor specifications figure 8-9. 4-pin fan cable connec tor (for active cek heat sink)
boxed processor specifications 112 figure 8-10. 4-pin base board fan header (for active cek heat sink)
113 boxed processor specifications 8.2.2 boxed processo r heat sink weight 8.2.2.1 thermal solution weight the 1u passive/3u+ active combination heat sink solution and the 2u passive heat sink solution will not exceed a mass of 1050 grams. note that this is per processor, a dual processor system will have up to 2010 grams total mass in the heat sinks. this large mass will require a minimum chassis stiffness to be met in order to withstand force during shock and vibration. see chapter 3 for details on the processor weight. 8.2.3 boxed processor retent ion mechanism and heat sink support (cek) baseboards and chassis designed for use by a system integrator should include holes that are in proper alignment with each other to support the boxed processor. refer to the server system infrastructure specification (ssi-eeb 3.6, teb 2.1 or ceb 1.1). these specification can be found at: http://www.ssiforum.org. figure 8-3 illustrates the common enabling kit (c ek) retention solution. the cek is designed to extend air-cooling capability th rough the use of larger heat sinks with minimal airflow blockage and bypass. cek retention mechanisms can allow the use of much heavier heat sink masses compared to legacy limits by using a load path directly attached to the chassis pan. the cek spring on the secondary side of the baseboard provides the necessary compressive load for the thermal interface material. the baseboard is intended to be isolated such that the dynamic loads from the heat sink are transferred to the chassis pan via the stif f screws and standoffs. the retention scheme reduces the risk of package pullout and solder joint failures. all components of the cek heat sink solution will be captive to the heat sink and will only require a phillips screwdriver to attach to the chassis pan. when installing the cek, the cek screws should be tightened un til they will no longer turn easily. this should represent approximately 6-8 inch-p ounds of torque. more than that may damage the retention mechanism components. 8.3 electrical requirements 8.3.1 fan power supply (active cek) the 4-pin pwm controlled thermal solution is being offered to help provide better control over pedestal chassis acoustics. this is achieved though more accurate measurement of processor die temperature through the processor?s digital thermal sensors. fan rpm is modulated through the use of an asic located on the baseboard, that sends out a pwm control signal to the 4th pin of the connector labeled as control. this thermal solution requires a constant + 12 v supplied to pin 2 of the active thermal solution and does not support variable voltage control or 3-pin pwm control. see ta b l e 8 - 2 for details on the 4-pin active heat sink solution connectors. if the 4-pin active fan heat sink solution is connected to an older 3-pin baseboard cpu fan header it will default back to a thermistor controlled mode, allowing compatibility with legacy 3-wire designs. when operatin g in thermistor controlled mode, fan rpm is automatically varied based on the tinlet temperature measured by a thermistor located at the fan inlet of the heat sink solution.
boxed processor specifications 114 the fan power header on the baseboard must be positioned to allow the fan heat sink power cable to reach it. the fan power head er identification and location must be documented in the suppliers platform documentation, or on the baseboard itself. the baseboard fan power header should be positioned within 177.8 mm [7 in.] from the center of the processor socket. 8.3.2 boxed processor cooling requirements as previously stated the boxed processor will be available in two product configurations. each configuration will requ ire unique design considerations. meeting the processor?s temperature specifications is also the function of the thermal design of the entire system, and ultimately the resp onsibility of the system integrator. the processor temperature specifications are found in chapter 6 of this document. 8.3.2.1 1u passive/3u+ active combinat ion heat sink solution (1u rack passive) in the 1u configuration it is assumed that a chassis duct will be implemented to provide a minimum airflow of 15 cfm at 0.38 in. h 2 o (25.5 m 3 /hr at 94.6 pa) of flow impedance. the duct should be carefully designed to minimize the airflow bypass table 8-1. pwm fan frequency specificatio ns for 4-pin active cek thermal solution description min frequency nominal frequency max frequency unit pwm control frequency range 21,000 25,000 28,000 hz table 8-2. fan specifications for 4-pin active cek thermal solution description min typ steady max steady max startup unit +12 v: 12 volt fan power supply 10.8 12 12 13.2 v ic: fan current draw n/a 1 1.25 1.5 a sense: sense frequency 2 2 2 2 pulses per fan revolution figure 8-11. fan cable connector pin ou t for 4-pin active cek thermal solution table 8-3. fan cable connector pin out for 4-pin active cek thermal solution pin number signal color 1 ground black 2 power: (+12 v) yellow 3 sense: 2 pulses per revolution green 4 control: 21 khz-28 khz blue
115 boxed processor specifications around the heatsink. it is assumed that a 40c t la is met. this requires a superior chassis design to limit the t rise at or below 5c with an external ambient temperature of 35c. these specifications apply to both copper and aluminum heatsink solutions. following these guidelines allows the de signer to meet quad-core intel? xeon? processor 5400 series thermal profile and co nform to the thermal requirements of the processor. 8.3.2.2 1u passive/3u+ active combinat ion heat sink solution (pedestal active) the active configuration of the combination solution is designed to help pedestal chassis users to meet the thermal processor requirements without the use of chassis ducting. it may be still be necessary to impl ement some form of chassis air guide or air duct to meet the t la temperature of 40 c depending on the pedestal chassis layout. also, while the active thermal solution design will mechanically fit into a 2u volumetric, it may not provide adequate airflow. this is due to the requirement of additional space at the top of the thermal solution to allow sufficient airflow into the heat sink fan. use of the active configuration in a 2u rackmount chassis is not recommended. it is recommended that the ambient air temperature outside of the chassis be kept at or below 35c. the air passing directly over the processor thermal solution should not be preheated by other system componen ts. meeting the processor?s temperature specification is the responsibility of the system integrator. 8.3.2.3 2u passive heat sink solu tion (2u+ rack or pedestal) in the 2u+ passive configuration, it is assu med that a chassis duct will be implemented to provide a minimum airflow of 27 cfm at 0.182 in. h 2 o (45.9 m 3 /hr at 45.3 pa) of flow impedance. the duct should be carefu lly designed to minimize the airflow bypass around the heatsink. these specifications ap ply to both copper and aluminum heatsink solutions. the t la temperature of 40 c should be met. this may require the use of superior design techniques to keep t rise at or below 5c based on an ambient external temperature of 35c. 8.4 boxed processor contents a direct chassis attach method must be us ed to avoid problems related to shock and vibration. the board must not bend beyond specification in order to avoid damage. the boxed processor contains the components necessary to solve both issues. the boxed processor will include the following items: ? quad-core intel? xeon? processor 5400 series ? unattached heat sink solution ? four screws, four springs, and four heat si nk standoffs (all captive to the heat sink) ? foam air bypass pad and skirt (included with 1u passive/3u+ active solution) ? thermal interface material (pre-applied on heat sink) ? installation and warranty manual ?intel inside logo other items listed in figure 8-3 that are required to complete this solution will be shipped with either the chassis or boards. they are as follows: ? cek spring (supplied by baseboard vendors) ? chassis standoffs (supplied by chassis vendors)
boxed processor specifications 116
117 debug tools specifications 9 debug tools specifications please refer to the appropriate platform de sign guidelines for information regarding debug tool specifications. section 1.3 provides collateral details. 9.1 debug port system requirements the quad-core intel? xeon? processor 5400 series debug port is the command and control interface for the in-target probe (itp) debugger. the itp enables run-time control of the processors for system debug. the debug port, which is connected to the fsb, is a combination of the system, jtag and execution signals. there are several mechanical, electrical and functional constraints on the debug port that must be followed. the mechanical constraint requires the debug port connector to be installed in the system with adequate physical clearance. electrical constraints exist due to the mixed high and low speed signals of the debug port for the processor. while the jtag signals operate at a maximum of 75 mhz, the execution signals operate at the common clock fsb frequency. the functional constraint requires the debug port to use the jtag system via a handshake and multiplexing scheme. in general, the information in this chapter may be used as a basis for including all run- control tools in quad-core intel? xeon? processor 5400 series-based system designs including tools from vendors other than intel. note: the debug port and jtag signal chain must be designed into the processor board to utilize the xdp for debug purposes except for interposer solutions. 9.2 target system implementation 9.2.1 system implementation specific connectivity and layout guidelines for the debug port are provided in the appropriate platform design guidelines. 9.3 logic analyzer interface (lai) intel is working with two logic analyzer ve ndors to provide logic analyzer interfaces (lais) for use in debugging quad-core inte l? xeon? processor 5400 series systems. tektronix and agilent should be contacted to obtain specific information about their logic analyzer interfaces. the following in formation is general in nature. specific information must be obtained fr om the logic analyzer vendor. due to the complexity of quad-core intel? xeon? processor 5400 series-based multiprocessor systems, the lai is critical in providing the ability to probe and capture fsb signals. there are two sets of consider ations to keep in mind when designing a quad-core intel? xeon? processor 5400 series-based system that can make use of an lai: mechanical and electrical.
debug tools specifications 118 9.3.1 mechanical considerations the lai is installed between the processor so cket and the processor. the lai plugs into the socket, while the processor plugs into a socket on the lai. cabling that is part of the lai egresses the system to allow an electrical connection between the processor and a logic analyzer. the maximum volume occupied by the lai, known as the keepout volume, as well as the cable egress restrict ions, should be obtained from the logic analyzer vendor. system designers must ma ke sure that the keepout volume remains unobstructed inside the system. note that it is possible that the keepout volume reserved for the lai may include differeren t requirements from the space normally occupied by the heatsink. if this is the ca se, the logic analyzer vendor will provide a cooling solution as part of the lai. 9.3.2 electrical considerations the lai will also affect the electrical performance of the fsb, therefore it is critical to obtain electrical load models from each of the logic analyzer vendors to be able to run system level simulations to prove that thei r tool will work in the system. contact the logic analyzer vendor for electrical specific ations and load models for the lai solution they provide.
intel? xeon? processor 5400 series, features ? united states l worldwide l about intel l press room l contact us l l l l l intel? reseller center products & platforms desktop notebook server services purchasing information member promotions sales & marketing training & events support & downloads program membership my account select a language http://www.intel.com/cd/channel/reseller/asmo-na/e...products/server/processors/q5400/feature/index.htm (1 of 6) [17-feb-2009 6:38:13 am]
intel? xeon? processor 5400 series, features intel? reseller center ? products & platforms ? server ? server processor ? intel? xeon? processor 5400 series ? features intel? xeon? processor 5400 series login id: password: log on forgot your login id? forgot your password? log on automatically more innovation - improved value now featuring intel's second-generation quad-core processor, existing mainstream server platforms, new high-performance computing (hpc) systems, new workstations, and new business servers each delivers a unique combination of technology targeted at specific it use environments. by selecting a platform that is best tuned for the most common it usages, intel? servers are able to better optimize return on investment while extending the leading performance and performance-per-watt advantages enjoyed when using intel's proven multi-core technology. intel? xeon? processor 5400 1 series help provide your data center or business with the performance headroom needed to confidently consolidate applications onto fewer systems using proven virtualization solutions or the compute power necessary for high-performance computing applications and workstation solutions. product matrix features and benefits thermal solution guide intel xeon processor 5400 series: build success into your business performance performance: l up to 25 percent better performance than previous generation quad-core 2 l up to 2x better performance than dual-core 3 l up to 5x increased performance over single-core 4 energy efficiency: l up to 38 percent improvement in performance per watt vs. previous generation 5 l 3 ghz quad-core at 80w l lower idle power reduces system power reliability: l intel-based servers have been a foundation of business technology for nearly 30 years and are built with more reliability features than completive alternatives for competitive application benchmarks please visit http://www.intel.com/performance/server/xeon/server.htm?iid=perf_serv_dp_sum+server the intel xeon processor 5400 series is compatible with intel? 5400, 5100, 5000p, 5000v and 5000x series of chipsets. server boards based on these chipsets are optimized for quad core with advanced platform features of dual independent bus and fully buffered dimm memory technology offering up to 4x available bandwidth of current generation platforms. improved i/o performance is possible with pci express* and the option of intel? i/o acceleration technology. the intel? xeon? processor 5200 1 series is also available for those applications which are not able to take advantage of more than two processing cores, and offers compelling performance and power efficiency at an entry price point for two-socket servers and workstations. product briefs l intel? xeon? processor 5400 series product brief (pdf 989kb) http://www.intel.com/cd/channel/reseller/asmo-na/e...products/server/processors/q5400/feature/index.htm (2 of 6) [17-feb-2009 6:38:13 am]
intel? xeon? processor 5400 series, features l intel xeon processor 5400 series animated product brief (pdf 5.84mb) server video demos l intel xeon processor 5000 sequence boxed intel? xeon processor 5400 series product matrix boxed product code heatsink process processor number frequency (tdp) fsb (mhz) cache number of cores dbs vt flexmigration 9 at80574kl096n (tray only) not included 45nm x5492 3.40 ghz (150w) 1600 12m total 4 y y y eu80574kl088n (tray only) not included 45nm x5482 3.20 ghz (150w) 1600 12m total 4 y y y at80574kl088nt (tray only) not included 45nm x5482 3.20 ghz (120w) 1600 12m total 4 y y y eu80574kl080nt (tray only) not included 45nm x5472 3.00 ghz (120w) 1600 12m total 4 y y y eu80574kl080n (tray only) not included 45nm e5472 3.00 ghz (80w) 1600 12m total 4 y y y bx80574x5470p 2u passive 45nm x5470 3.33 ghz (120w) 1333 12m total 4 y y y bx80574x5470a active or 1u 45nm x5470 3.33 ghz (120w) 1333 12m total 4 y y y EU80574KL072N not included 45nm e5462 2.80 ghz (80w) 1600 12m total 4 y y y bx80574x5460p 2u passive 45nm x5460 3.16 ghz (120w) 1333 12m total 4 y y y bx80574x5460a active or 1u 45nm x5460 3.16 ghz (120w) 1333 12m total 4 y y y bx80574x5450p 2u passive 45nm x5450 3.00 ghz (120w) 1333 12m total 4 y y y bx80574x5450a active or 1u 45nm x5450 3.00 ghz (120w) 1333 12m total 4 y y y bx80574e5450p 2u passive 45nm e5450 3.00 ghz (80w) 1333 12m total 4 y y y bx80574e5450a active or 1u 45nm e5450 3.00 ghz (80w) 1333 12m total 4 y y y bx80574e5440p 2u passive 45nm e5440 2.83 ghz (80w) 1333 12m total 4 y y y bx80574e5440a active or 1u 45nm e5440 2.83 ghz (80w) 1333 12m total 4 y y y bx80574e5430p 2u passive 45nm e5430 2.66 ghz (80w) 1333 12m total 4 y y y bx80574e5430a active or 1u 45nm e5430 2.66 ghz (80w) 1333 12m total 4 y y y bx80574l5420p 2u passive 45nm l5420 2.50 ghz (50w) 1333 12m total 4 y y y bx80574l5420a active or 1u 45nm l5420 2.50 ghz (50w) 1333 12m total 4 y y y bx80574e5420p 2u passive 45nm e5420 2.50 ghz (80w) 1333 12m total 4 y y y bx80574e5420a active or 1u 45nm e5420 2.50 ghz (80w) 1333 12m total 4 y y y bx80574l5410p 2u passive 45nm l5410 2.33 ghz (50w) 1333 12m total 4 y y y bx80574l5410a active or 1u 45nm l5410 2.33 ghz (50w) 1333 12m total 4 y y y bx80574e5410p 2u passive 45nm e5410 2.33 ghz (80w) 1333 12m total 4 y y y bx80574e5410a active or 1u 45nm e5410 2.33 ghz (80w) 1333 12m total 4 y y y bx80574e5405p 2u passive 45nm e5405 2.00 ghz (80w) 1333 12m total 4 y y bx80574e5405a active or 1u 45nm e5405 2.00 ghz (80w) 1333 12m total 4 y y at80573kl0966m not included 45nm x5272 3.40 ghz (80w) 1600 6m total 2 y y y http://www.intel.com/cd/channel/reseller/asmo-na/e...products/server/processors/q5400/feature/index.htm (3 of 6) [17-feb-2009 6:38:13 am]
intel? xeon? processor 5400 series, features at80573kj1006m not included 45nm x5270 3.50 ghz (80w) 1333 6m total 2 y y y at80573kj0936m not included 45nm x5260 3.33 ghz (80w) 1333 6m total 2 y y y at80573jj0806m not included 45nm l5240 3.20 ghz (40w) 1333 6m total 2 y y y bx80574e5205a active or 1u 45nm e5205 1.86 ghz (65w) 1066 6m total 2 y y y bx80574e5205p 2u passive 45nm e5205 1.86 ghz (65w) 1066 6m total 2 y y y back to top intel? xeon? processor 5400 series features key features benefits multi-core processing l 45nm technology boosts performance on a range of workloads. l increased headroom for multi-threaded applications and heavy multi-tasking scenarios. l helps boost system utilization through virtualization and application responsiveness. enhanced intel? core? microarchitecture l boosts performance on multiple applications, user environments and data- demanding workloads, while enabling denser data center deployments through improved performance per watt. l the new 45nm enhanced intel core microarchitecture delivers up to 38 percent more performance per watt in the same platforms and at the same system power level. 6 l reduced idle processor power lowers average server power consumption. up to 12 mb of on-die l2 cache (2 x 6mb) l increases efficiency of l2 cache-to-core data transfers, maximizing main memory to processor bandwidth. l reduces latency by storing larger data sets closer to the processor, reducing the number of trips to main memory. l up to 6 mb of l2 cache can be allocated to one core. intel? virtualization technology 7 (intel? vt) l a suite of processor enhancements that assists virtualization software to deliver more efficient virtualization solutions and greater capabilities including 64-bit guest os support. fully buffered dimm (fbdimm) or native ddr2 registered dimm technology support (depending on chipset used) l flexibility to optimize system for performance and capacity or cost effectiveness and power efficiency. intel? i/o acceleration technology (intel? i/oat) with next generation improvements l next-generation improvements designed to significantly accelerate data processing across the entire platform through cpu utilization and latency improvements. enhanced front-side bus (fsb) l new dedicated high-speed bus design enables increased throughput and bandwidth between each of the processors and the chipset. l supporting from 1066 up to 1333 or 1600 mhz. intel? 64 architecture 8 l flexibility for 64-bit and 32-bit applications and operating systems. back to top boxed intel? xeon? processor 5400 series thermal solution guide http://www.intel.com/cd/channel/reseller/asmo-na/e...products/server/processors/q5400/feature/index.htm (4 of 6) [17-feb-2009 6:38:13 am]
intel? xeon? processor 5400 series, features ordering code thermal solution chassis bx80574xxxxxa 10 included with 120w cpus included with 80w and lower cpus non-ducted pedestal or 1u chassis examples: sc5299-e sr1500 sr1550 bx80574xxxxxp 10 included with 120w cpus included with 80w and lower cpus ducted pedestal or 2u chassis examples: sc5400 sr2500 back to top please refer to the integration overview for detailed boxed intel? xeon? processor installation instructions. please consult non-intel chassis manufacturer for specific boxed intel xeon processor compatibility information. benchmark for performance comparison for the intel xeon processor 5400 series: specint*_ rate2006: x5460 vs x5365 - published/measured results on specint*_ rate2006 - october 2, 2007 with 64-bit suse linux* enterprise server 10 16 gb (8x2 gb). spec binaries built with intel? compiler 10.1 for 32-bit/64-bit linux. 1 intel processor numbers are not a measure of performance. processor numbers differentiate features within each processor family, not across different processor families. see www.intel.com/products/processor_number for details. 2 intel? xeon? processor 5300 series ("ctn"). up to 25% (1.25x) higher performance x5460 vs x5365 - published/measured results on specjbb2005* - october 2, 07. 3 intel? xeon? processor 5100 series ("wdc"). up to 119% (2.19x) higher performance x5460 vs 5160 - published/measured results on specjbb2005* - oct 2, 07. 4 64-bit intel? xeon? processor 3.80ghz. up to 443% (5.43x) higher performance x5460 vs xeon 3.80 - published/ measured results on specint*_rate_base2006 - oct 2, 07. 5 intel? xeon? processor 5300 series ("ctn"). up to 38% (1.38x) higher perf/watt e5450 vs e5335 - published/measured results on specjbb2005* - oct 2, 07. 6 intel server pre-production platform with twointel? xeon? processor e5450 3.0 ghz, 2x6 mb l2 cache or e5335, 2x4 mb l2 cache, 1333 mhz system bus, 16 gb memory ddr2-667 fbdimm, microsoft windows server 2003 enterprise* x64 edition sp1 (64-bit), bea jrockit* 5.0 p27.2.0. intel internal measurement - september 2007. perf/watt calculated by dividing the performance by measured system power during steady state window. 7 intel? virtualization technology requires a computer system with an enabled intel? processor, bios, virtual machine monitor (vmm) and, for some uses, certain platform software enabled for it. functionality, performance or other benefits will vary depending on hardware and software configurations and may require a bios update. software applications may not be compatible with all operating systems. please check with your application vendor. 8 64-bit computing on intel architecture requires a computer system with a processor, chipset, bios, operating system, device drivers and applications enabled for intel? 64 architecture. performance will vary depending on your hardware and software configurations. consult with your system vendor for more information. performance and competitive information is accurate at time of document publication. for latest competitive and performance information, visit www.intel.com/performance. 9 backward compatibility for live vm migration also exists with current intel? core? microarchitecture products (xeon 5100 and xeon 3000) and forward compatibility with future dual and multi-core processors. contact your preferred vmm vendor for support requirements. 10 insert processor number where "xxxxx" is located (ex x5355) http://www.intel.com/cd/channel/reseller/asmo-na/e...products/server/processors/q5400/feature/index.htm (5 of 6) [17-feb-2009 6:38:13 am]
intel? xeon? processor 5400 series, features site maprssjobsinvestor relationspress roomcontact us terms of use*trademarksprivacy?intel corporation http://www.intel.com/cd/channel/reseller/asmo-na/e...products/server/processors/q5400/feature/index.htm (6 of 6) [17-feb-2009 6:38:13 am]

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